2009-03-04 04:28:35 +01:00
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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2012-03-08 06:13:49 +01:00
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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2009-03-04 04:28:35 +01:00
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****************************************************************************
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****************************************************************************/
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#ifndef __ASM_ARCH_OMAP_HARDWARE_H
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#define __ASM_ARCH_OMAP_HARDWARE_H
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#include <asm/sizes.h>
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#ifndef __ASSEMBLER__
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#include <asm/types.h>
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#include <asm/arch/cpu.h>
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#endif
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#include <asm/arch/io.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#include <asm/arch/serial.h>
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#define OMAP_MPU_TIMER1_BASE (0xfffec500)
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#define OMAP_MPU_TIMER2_BASE (0xfffec600)
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#define OMAP_MPU_TIMER3_BASE (0xfffec700)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MPU_TIMER_FREE (1 << 6)
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#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
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#define MPU_TIMER_AR (1 << 1)
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#define MPU_TIMER_ST (1 << 0)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define CLKGEN_REG_BASE (0xfffece00)
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#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
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#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
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#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
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#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
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#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
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#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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#define CK_RATEF 1
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#define CK_IDLEF 2
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#define CK_ENABLEF 4
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define CK_SELECTF 8
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#define SETARM_IDLE_SHIFT
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#define DPLL_CTL (0xfffecf00)
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#define DSP_CONFIG_REG_BASE (0xe1008000)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
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#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
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#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
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#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ULPD_REG_BASE (0xfffe0800)
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#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
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#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
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#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DIS_USB_PVCI_CLK (1 << 5)
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#define USB_MCLK_EN (1 << 4)
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#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
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#define SOFT_UDC_REQ (1 << 4)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define SOFT_USB_CLK_REQ (1 << 3)
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#define SOFT_DPLL_REQ (1 << 0)
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#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
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#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
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#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
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#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
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#define DIS_MMC2_DPLL_REQ (1 << 11)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DIS_MMC1_DPLL_REQ (1 << 10)
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#define DIS_UART3_DPLL_REQ (1 << 9)
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#define DIS_UART2_DPLL_REQ (1 << 8)
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#define DIS_UART1_DPLL_REQ (1 << 7)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DIS_USB_HOST_DPLL_REQ (1 << 6)
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#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
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#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
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#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
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#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MOD_CONF_CTRL_0 0xfffe1080
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#define MOD_CONF_CTRL_1 0xfffe1110
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#define FUNC_MUX_CTRL_0 0xfffe1000
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#define FUNC_MUX_CTRL_1 0xfffe1004
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FUNC_MUX_CTRL_2 0xfffe1008
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#define COMP_MODE_CTRL_0 0xfffe100c
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#define FUNC_MUX_CTRL_3 0xfffe1010
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#define FUNC_MUX_CTRL_4 0xfffe1014
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FUNC_MUX_CTRL_5 0xfffe1018
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#define FUNC_MUX_CTRL_6 0xfffe101C
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#define FUNC_MUX_CTRL_7 0xfffe1020
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#define FUNC_MUX_CTRL_8 0xfffe1024
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FUNC_MUX_CTRL_9 0xfffe1028
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#define FUNC_MUX_CTRL_A 0xfffe102C
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#define FUNC_MUX_CTRL_B 0xfffe1030
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#define FUNC_MUX_CTRL_C 0xfffe1034
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FUNC_MUX_CTRL_D 0xfffe1038
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#define PULL_DWN_CTRL_0 0xfffe1040
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#define PULL_DWN_CTRL_1 0xfffe1044
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#define PULL_DWN_CTRL_2 0xfffe1048
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PULL_DWN_CTRL_3 0xfffe104c
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#define PULL_DWN_CTRL_4 0xfffe10ac
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#define FUNC_MUX_CTRL_E 0xfffe1090
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#define FUNC_MUX_CTRL_F 0xfffe1094
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FUNC_MUX_CTRL_10 0xfffe1098
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#define FUNC_MUX_CTRL_11 0xfffe109c
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#define FUNC_MUX_CTRL_12 0xfffe10a0
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#define PU_PD_SEL_0 0xfffe10b4
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PU_PD_SEL_1 0xfffe10b8
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#define PU_PD_SEL_2 0xfffe10bc
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#define PU_PD_SEL_3 0xfffe10c0
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#define PU_PD_SEL_4 0xfffe10c4
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP_TIMER32K_BASE 0xFFFBC400
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#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
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#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
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#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
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#define MPUI_BASE (0xfffec900)
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#define MPUI_CTRL (MPUI_BASE + 0x0)
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#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
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#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
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#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
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#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
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#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
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#define OMAP_LPG1_BASE 0xfffbd000
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#define OMAP_LPG2_BASE 0xfffbd800
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
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#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
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#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
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#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP_PWL_BASE 0xfffb5800
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#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
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#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
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#include "omap730.h"
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#include "omap1510.h"
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#include "omap24xx.h"
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#include "omap16xx.h"
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#ifndef __ASSEMBLER__
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#endif
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