Merge "bionic: arm64: generic: strcmp: align to 64B cache line"
am: f785a6cbff
Change-Id: I3b5b76a6c9a0881c9f82012161254dbd480d062b
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@ -57,6 +57,7 @@
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/* Start of performance-critical section -- one 64B cache line. */
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ENTRY(strcmp)
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.p2align 6
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eor tmp1, src1, src2
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mov zeroones, #REP8_01
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tst tmp1, #7
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