Merge "[AArch64] Optimized memcmp"
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Treehugger Robot
Gerrit Code Review
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1414802f93
2 changed files with 127 additions and 125 deletions
28
libc/NOTICE
28
libc/NOTICE
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@ -5643,6 +5643,34 @@ SUCH DAMAGE.
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-------------------------------------------------------------------
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Copyright (c) 2017 ARM Ltd
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. The name of the company may not be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-------------------------------------------------------------------
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Copyright (c) 2017 Imagination Technologies.
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All rights reserved.
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@ -1,33 +1,34 @@
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/* Copyright (c) 2014, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2017 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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* ARMv8-a, AArch64, unaligned accesses.
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*/
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#include <private/bionic_asm.h>
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@ -36,120 +37,93 @@
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#define src1 x0
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#define src2 x1
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#define limit x2
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#define result x0
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#define result w0
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/* Internal variables. */
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#define data1 x3
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#define data1w w3
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#define data2 x4
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#define data2w w4
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#define has_nul x5
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#define diff x6
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#define endloop x7
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#define tmp1 x8
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#define tmp2 x9
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#define tmp3 x10
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#define pos x11
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#define limit_wd x12
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#define mask x13
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#define tmp1 x5
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/* Small inputs of less than 8 bytes are handled separately. This allows the
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main code to be sped up using unaligned loads since there are now at least
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8 bytes to be compared. If the first 8 bytes are equal, align src1.
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This ensures each iteration does at most one unaligned access even if both
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src1 and src2 are unaligned, and mutually aligned inputs behave as if
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aligned. After the main loop, process the last 8 bytes using unaligned
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accesses. */
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.p2align 6
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ENTRY(memcmp)
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cbz limit, .Lret0
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eor tmp1, src1, src2
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tst tmp1, #7
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b.ne .Lmisaligned8
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ands tmp1, src1, #7
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b.ne .Lmutual_align
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add limit_wd, limit, #7
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lsr limit_wd, limit_wd, #3
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/* Start of performance-critical section -- one 64B cache line. */
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.Lloop_aligned:
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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.Lstart_realigned:
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subs limit_wd, limit_wd, #1
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eor diff, data1, data2 /* Non-zero if differences found. */
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csinv endloop, diff, xzr, ne /* Last Dword or differences. */
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cbz endloop, .Lloop_aligned
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/* End of performance-critical section -- one 64B cache line. */
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subs limit, limit, 8
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b.lo .Lless8
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/* Not reached the limit, must have found a diff. */
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cbnz limit_wd, .Lnot_limit
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/* Limit >= 8, so check first 8 bytes using unaligned loads. */
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ldr data1, [src1], 8
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ldr data2, [src2], 8
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and tmp1, src1, 7
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add limit, limit, tmp1
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cmp data1, data2
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bne .Lreturn
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/* Limit % 8 == 0 => all bytes significant. */
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ands limit, limit, #7
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b.eq .Lnot_limit
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/* Align src1 and adjust src2 with bytes not yet done. */
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sub src1, src1, tmp1
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sub src2, src2, tmp1
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lsl limit, limit, #3 /* Bits -> bytes. */
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mov mask, #~0
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#ifdef __AARCH64EB__
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lsr mask, mask, limit
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#else
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lsl mask, mask, limit
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#endif
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bic data1, data1, mask
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bic data2, data2, mask
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subs limit, limit, 8
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b.ls .Llast_bytes
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orr diff, diff, mask
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.Lnot_limit:
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/* Loop performing 8 bytes per iteration using aligned src1.
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Limit is pre-decremented by 8 and must be larger than zero.
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Exit if <= 8 bytes left to do or if the data is not equal. */
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.p2align 4
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.Lloop8:
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ldr data1, [src1], 8
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ldr data2, [src2], 8
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subs limit, limit, 8
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ccmp data1, data2, 0, hi /* NZCV = 0b0000. */
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b.eq .Lloop8
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cmp data1, data2
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bne .Lreturn
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/* Compare last 1-8 bytes using unaligned access. */
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.Llast_bytes:
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ldr data1, [src1, limit]
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ldr data2, [src2, limit]
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/* Compare data bytes and set return value to 0, -1 or 1. */
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.Lreturn:
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#ifndef __AARCH64EB__
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rev diff, diff
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rev data1, data1
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rev data2, data2
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#endif
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/* The MS-non-zero bit of DIFF marks either the first bit
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that is different, or the end of the significant data.
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Shifting left now will bring the critical information into the
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top bits. */
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clz pos, diff
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lsl data1, data1, pos
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lsl data2, data2, pos
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/* But we need to zero-extend (char is unsigned) the value and then
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perform a signed 32-bit subtraction. */
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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cmp data1, data2
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.Lret_eq:
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cset result, ne
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cneg result, result, lo
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ret
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.Lmutual_align:
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/* Sources are mutually aligned, but are not currently at an
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alignment boundary. Round down the addresses and then mask off
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the bytes that precede the start point. */
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bic src1, src1, #7
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bic src2, src2, #7
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add limit, limit, tmp1 /* Adjust the limit for the extra. */
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lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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ldr data1, [src1], #8
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neg tmp1, tmp1 /* Bits to alignment -64. */
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ldr data2, [src2], #8
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mov tmp2, #~0
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#ifdef __AARCH64EB__
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/* Big-endian. Early bytes are at MSB. */
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lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#else
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/* Little-endian. Early bytes are at LSB. */
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lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#endif
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add limit_wd, limit, #7
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orr data1, data1, tmp2
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orr data2, data2, tmp2
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lsr limit_wd, limit_wd, #3
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b .Lstart_realigned
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.Lret0:
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mov result, #0
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ret
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.p2align 6
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.Lmisaligned8:
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sub limit, limit, #1
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1:
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/* Perhaps we can do better than this. */
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ldrb data1w, [src1], #1
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ldrb data2w, [src2], #1
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subs limit, limit, #1
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ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
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b.eq 1b
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sub result, data1, data2
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.p2align 4
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/* Compare up to 8 bytes. Limit is [-8..-1]. */
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.Lless8:
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adds limit, limit, 4
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b.lo .Lless4
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ldr data1w, [src1], 4
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ldr data2w, [src2], 4
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cmp data1w, data2w
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b.ne .Lreturn
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sub limit, limit, 4
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.Lless4:
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adds limit, limit, 4
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beq .Lret_eq
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.Lbyte_loop:
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ldrb data1w, [src1], 1
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ldrb data2w, [src2], 1
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subs limit, limit, 1
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ccmp data1w, data2w, 0, ne /* NZCV = 0b0000. */
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b.eq .Lbyte_loop
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sub result, data1w, data2w
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ret
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END(memcmp)
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