Switch arch-mips64/include/machine to a symlink.
Imagination already did the work to make the contents of these directories identical. Let's take advantage of that fact. Change-Id: Ib101ba39041fb500c9c618fa2020e72aa2ccd9c2
This commit is contained in:
Elliott Hughes
parent
af829f2de9
commit
2fecbfaeee
7 changed files with 1 additions and 659 deletions
1
libc/arch-mips64/include/machine
Symbolic link
1
libc/arch-mips64/include/machine
Symbolic link
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@ -0,0 +1 @@
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../../arch-mips/include/machine
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@ -1,206 +0,0 @@
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/* $OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */
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/*
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* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _MIPS64_ASM_H
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#define _MIPS64_ASM_H
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#define __bionic_asm_align 4
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#undef __bionic_asm_custom_entry
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#undef __bionic_asm_custom_end
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#define __bionic_asm_custom_entry(f) .ent f
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#define __bionic_asm_custom_end(f) .end f
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#include <machine/regdef.h>
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#define _MIPS_ISA_MIPS1 1 /* R2000/R3000 */
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#define _MIPS_ISA_MIPS2 2 /* R4000/R6000 */
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#define _MIPS_ISA_MIPS3 3 /* R4000 */
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#define _MIPS_ISA_MIPS4 4 /* TFP (R1x000) */
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#define _MIPS_ISA_MIPS5 5
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#define _MIPS_ISA_MIPS32 6
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#define _MIPS_ISA_MIPS64 7
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#if !defined(ABICALLS) && !defined(_NO_ABICALLS)
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#define ABICALLS .abicalls
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#endif
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#if defined(ABICALLS) && !defined(_KERNEL)
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ABICALLS
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#endif
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#if !defined(__MIPSEL__) && !defined(__MIPSEB__)
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#error "__MIPSEL__ or __MIPSEB__ must be defined"
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#endif
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/*
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* Define how to access unaligned data word
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*/
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#if defined(__MIPSEL__)
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#define LWLO lwl
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#define LWHI lwr
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#define SWLO swl
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#define SWHI swr
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#define LDLO ldl
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#define LDHI ldr
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#define SDLO sdl
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#define SDHI sdr
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#endif
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#if defined(__MIPSEB__)
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#define LWLO lwr
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#define LWHI lwl
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#define SWLO swr
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#define SWHI swl
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#define LDLO ldr
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#define LDHI ldl
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#define SDLO sdr
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#define SDHI sdl
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#endif
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/*
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* Define programming environment for ABI.
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*/
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#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE)
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#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)
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#define NARGSAVE 4
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#define SETUP_GP \
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.set noreorder; \
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.cpload t9; \
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.set reorder;
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#define SAVE_GP(x) \
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.cprestore x
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#define SETUP_GP64(gpoff, name)
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#define RESTORE_GP64
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#endif
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#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
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#define NARGSAVE 0
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#define SETUP_GP
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#define SAVE_GP(x)
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#define SETUP_GP64(gpoff, name) \
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.cpsetup t9, gpoff, name
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#define RESTORE_GP64 \
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.cpreturn
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#endif
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#define MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31))
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#else /* defined(ABICALLS) && !defined(_KERNEL) */
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#define NARGSAVE 4
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#define SETUP_GP
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#define SAVE_GP(x)
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#define ALIGNSZ 16 /* Stack layout alignment */
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#define FRAMESZ(sz) (((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1))
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#endif
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/*
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* Basic register operations based on selected ISA
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*/
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#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS32)
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#define REGSZ 4 /* 32 bit mode register size */
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#define LOGREGSZ 2 /* log rsize */
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#define REG_S sw
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#define REG_L lw
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#define CF_SZ 24 /* Call frame size */
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#define CF_ARGSZ 16 /* Call frame arg size */
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#define CF_RA_OFFS 20 /* Call ra save offset */
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#endif
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#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS64)
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#define REGSZ 8 /* 64 bit mode register size */
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#define LOGREGSZ 3 /* log rsize */
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#define REG_S sd
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#define REG_L ld
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#define CF_SZ 48 /* Call frame size (multiple of ALIGNSZ) */
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#define CF_ARGSZ 32 /* Call frame arg size */
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#define CF_RA_OFFS 40 /* Call ra save offset */
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#endif
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#define REGSZ_FP 8 /* 64 bit FP register size */
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#ifndef __LP64__
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#define PTR_L lw
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#define PTR_S sw
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#define PTR_SUB sub
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#define PTR_ADD add
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#define PTR_SUBU subu
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#define PTR_ADDU addu
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#define LI li
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#define LA la
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#define PTR_SLL sll
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#define PTR_SRL srl
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#define PTR_VAL .word
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#else
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#define PTR_L ld
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#define PTR_S sd
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#define PTR_ADD dadd
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#define PTR_SUB dsub
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#define PTR_SUBU dsubu
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#define PTR_ADDU daddu
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#define LI dli
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#define LA dla
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#define PTR_SLL dsll
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#define PTR_SRL dsrl
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#define PTR_VAL .dword
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#endif
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/*
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* LEAF(x, fsize)
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*
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* Declare a leaf routine.
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*/
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#define LEAF(x, fsize) \
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.align 3; \
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.globl x; \
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.ent x, 0; \
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x: ; \
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.cfi_startproc; \
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.frame sp, fsize, ra; \
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SETUP_GP \
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/*
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* NON_LEAF(x)
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*
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* Declare a non-leaf routine (a routine that makes other C calls).
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*/
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#define NON_LEAF(x, fsize, retpc) \
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.align 3; \
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.globl x; \
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.ent x, 0; \
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x: ; \
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.cfi_startproc; \
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.frame sp, fsize, retpc; \
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SETUP_GP \
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#endif /* !_MIPS_ASM_H */
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@ -1,196 +0,0 @@
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/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */
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#ifndef _MIPS_ELF_MACHDEP_H_
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#define _MIPS_ELF_MACHDEP_H_
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#ifdef _LP64
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#define ARCH_ELFSIZE 64 /* MD native binary size */
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#else
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#define ARCH_ELFSIZE 32 /* MD native binary size */
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#endif
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#if ELFSIZE == 32
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#define ELF32_MACHDEP_ID_CASES \
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case EM_MIPS: \
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break;
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#define ELF32_MACHDEP_ID EM_MIPS
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#elif ELFSIZE == 64
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#define ELF64_MACHDEP_ID_CASES \
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case EM_MIPS: \
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break;
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#define ELF64_MACHDEP_ID EM_MIPS
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#endif
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/* mips relocs. */
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#define R_MIPS_NONE 0
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#define R_MIPS_16 1
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#define R_MIPS_32 2
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#define R_MIPS_REL32 3
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#define R_MIPS_REL R_MIPS_REL32
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#define R_MIPS_26 4
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#define R_MIPS_HI16 5 /* high 16 bits of symbol value */
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#define R_MIPS_LO16 6 /* low 16 bits of symbol value */
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#define R_MIPS_GPREL16 7 /* GP-relative reference */
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#define R_MIPS_LITERAL 8 /* Reference to literal section */
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#define R_MIPS_GOT16 9 /* Reference to global offset table */
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#define R_MIPS_GOT R_MIPS_GOT16
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#define R_MIPS_PC16 10 /* 16 bit PC relative reference */
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#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */
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#define R_MIPS_CALL R_MIPS_CALL16
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#define R_MIPS_GPREL32 12
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/* 13, 14, 15 are not defined at this point. */
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#define R_MIPS_UNUSED1 13
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#define R_MIPS_UNUSED2 14
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#define R_MIPS_UNUSED3 15
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/*
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* The remaining relocs are apparently part of the 64-bit Irix ELF ABI.
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*/
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#define R_MIPS_SHIFT5 16
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#define R_MIPS_SHIFT6 17
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#define R_MIPS_64 18
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#define R_MIPS_GOT_DISP 19
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#define R_MIPS_GOT_PAGE 20
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#define R_MIPS_GOT_OFST 21
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#define R_MIPS_GOT_HI16 22
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#define R_MIPS_GOT_LO16 23
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#define R_MIPS_SUB 24
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#define R_MIPS_INSERT_A 25
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#define R_MIPS_INSERT_B 26
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#define R_MIPS_DELETE 27
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#define R_MIPS_HIGHER 28
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#define R_MIPS_HIGHEST 29
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#define R_MIPS_CALL_HI16 30
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#define R_MIPS_CALL_LO16 31
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#define R_MIPS_SCN_DISP 32
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#define R_MIPS_REL16 33
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#define R_MIPS_ADD_IMMEDIATE 34
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#define R_MIPS_PJUMP 35
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#define R_MIPS_RELGOT 36
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#define R_MIPS_JALR 37
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/* TLS relocations */
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#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */
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#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */
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#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */
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#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */
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#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */
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#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */
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#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */
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#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */
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#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */
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#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */
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#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */
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#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
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#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
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#define R_MIPS_max 51
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#define R_TYPE(name) __CONCAT(R_MIPS_,name)
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#define R_MIPS16_min 100
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#define R_MIPS16_26 100
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#define R_MIPS16_GPREL 101
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#define R_MIPS16_GOT16 102
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#define R_MIPS16_CALL16 103
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#define R_MIPS16_HI16 104
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#define R_MIPS16_LO16 105
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#define R_MIPS16_max 106
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/* mips dynamic tags */
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#define DT_MIPS_RLD_VERSION 0x70000001
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#define DT_MIPS_TIME_STAMP 0x70000002
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#define DT_MIPS_ICHECKSUM 0x70000003
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#define DT_MIPS_IVERSION 0x70000004
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#define DT_MIPS_FLAGS 0x70000005
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#define DT_MIPS_BASE_ADDRESS 0x70000006
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#define DT_MIPS_CONFLICT 0x70000008
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#define DT_MIPS_LIBLIST 0x70000009
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#define DT_MIPS_CONFLICTNO 0x7000000b
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#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */
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#define DT_MIPS_LIBLISTNO 0x70000010
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#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */
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#define DT_MIPS_UNREFEXTNO 0x70000012
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#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */
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#define DT_MIPS_HIPAGENO 0x70000014
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#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */
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/*
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* ELF Flags
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*/
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#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */
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#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */
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#define EF_MIPS_ABI2 0x00000020 /* N32 */
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#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */
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#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */
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#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */
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#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */
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#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */
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#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */
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#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */
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#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */
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#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */
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#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
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#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */
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#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */
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#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */
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#define EF_MIPS_ABI 0x0000f000
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#define EF_MIPS_ABI_O32 0x00001000
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#define EF_MIPS_ABI_O64 0x00002000
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#define EF_MIPS_ABI_EABI32 0x00003000
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#define EF_MIPS_ABI_EABI64 0x00004000
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#if defined(__MIPSEB__)
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#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB
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#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB
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#elif defined(__MIPSEL__)
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#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
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#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB
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#elif !defined(HAVE_NBTOOL_CONFIG_H)
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#error neither __MIPSEL__ nor __MIPSEB__ are defined.
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#endif
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#ifdef _KERNEL
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#ifdef _KERNEL_OPT
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#include "opt_compat_netbsd.h"
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#endif
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#ifdef COMPAT_16
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/*
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* Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable.
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* Tell the kernel ELF exec code not to try relocating the interpreter
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* for dynamically-linked ELF binaries.
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*/
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#define ELF_INTERP_NON_RELOCATABLE
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#endif /* COMPAT_16 */
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/*
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* We need to be able to include the ELF header so we can pick out the
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* ABI being used.
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*/
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#ifdef ELFSIZE
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#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe)
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#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup)
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#endif
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struct exec_package;
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int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *,
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vaddr_t *);
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void coredump_elf32_setup(struct lwp *, void *);
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int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *,
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vaddr_t *);
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void coredump_elf64_setup(struct lwp *, void *);
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#endif /* _KERNEL */
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#endif /* _MIPS_ELF_MACHDEP_H_ */
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@ -1,66 +0,0 @@
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/* $OpenBSD: endian.h,v 1.5 2006/02/27 23:35:59 miod Exp $ */
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|
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/*
|
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* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MIPS64_ENDIAN_H_
|
||||
#define _MIPS64_ENDIAN_H_
|
||||
|
||||
#ifdef __GNUC__
|
||||
|
||||
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
#define __swap16md(x) ({ \
|
||||
register uint16_t _x = (x); \
|
||||
register uint16_t _r; \
|
||||
__asm volatile ("wsbh %0, %1" : "=r" (_r) : "r" (_x)); \
|
||||
_r; \
|
||||
})
|
||||
|
||||
#define __swap32md(x) ({ \
|
||||
register uint32_t _x = (x); \
|
||||
register uint32_t _r; \
|
||||
__asm volatile ("wsbh %0, %1; rotr %0, %0, 16" : "=r" (_r) : "r" (_x)); \
|
||||
_r; \
|
||||
})
|
||||
|
||||
#define __swap64md(x) ({ \
|
||||
uint64_t _swap64md_x = (x); \
|
||||
(uint64_t) __swap32md(_swap64md_x >> 32) | \
|
||||
(uint64_t) __swap32md(_swap64md_x & 0xffffffff) << 32; \
|
||||
})
|
||||
|
||||
/* Tell sys/endian.h we have MD variants of the swap macros. */
|
||||
#define MD_SWAP
|
||||
|
||||
#endif /* __mips32r2__ */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#define _BYTE_ORDER _LITTLE_ENDIAN
|
||||
#define __STRICT_ALIGNMENT
|
||||
#include <sys/types.h>
|
||||
#include <sys/endian.h>
|
||||
|
||||
#endif /* _MIPS64_ENDIAN_H_ */
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
/* $OpenBSD: regdef.h,v 1.3 2005/08/07 07:29:44 miod Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* Ralph Campbell. This file is derived from the MIPS RISC
|
||||
* Architecture book by Gerry Kane.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)regdef.h 8.1 (Berkeley) 6/10/93
|
||||
*/
|
||||
#ifndef _MIPS_REGDEF_H_
|
||||
#define _MIPS_REGDEF_H_
|
||||
|
||||
#if (_MIPS_SIM == _ABI64) && !defined(__mips_n64)
|
||||
#define __mips_n64 1
|
||||
#endif
|
||||
#if (_MIPS_SIM == _ABIN32) && !defined(__mips_n32)
|
||||
#define __mips_n32 1
|
||||
#endif
|
||||
|
||||
#define zero $0 /* always zero */
|
||||
#define AT $at /* assembler temp */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#if defined(__mips_n32) || defined(__mips_n64)
|
||||
#define a4 $8 /* expanded register arguments */
|
||||
#define a5 $9
|
||||
#define a6 $10
|
||||
#define a7 $11
|
||||
#define ta0 $8 /* alias */
|
||||
#define ta1 $9
|
||||
#define ta2 $10
|
||||
#define ta3 $11
|
||||
#define t0 $12 /* temp registers (not saved across subroutine calls) */
|
||||
#define t1 $13
|
||||
#define t2 $14
|
||||
#define t3 $15
|
||||
#else
|
||||
#define t0 $8 /* temp registers (not saved across subroutine calls) */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define ta0 $12 /* alias */
|
||||
#define ta1 $13
|
||||
#define ta2 $14
|
||||
#define ta3 $15
|
||||
#endif
|
||||
#define s0 $16 /* saved across subroutine calls (callee saved) */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* two more temp registers */
|
||||
#define t9 $25
|
||||
#define k0 $26 /* kernel temporary */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define s8 $30 /* one more callee saved */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
#endif /* !_MIPS_REGDEF_H_ */
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* $OpenBSD: setjmp.h,v 1.2 2004/08/10 21:10:56 pefo Exp $ */
|
||||
|
||||
/* Public domain */
|
||||
|
||||
#ifndef _MIPS_SETJMP_H_
|
||||
#define _MIPS_SETJMP_H_
|
||||
|
||||
#ifdef __LP64__
|
||||
#define _JBLEN 22 /* size, in 8-byte longs, of a mips64 jmp_buf */
|
||||
#else
|
||||
#define _JBLEN 29 /* size, in 4-byte longs, of a mips32 jmp_buf */
|
||||
#endif
|
||||
|
||||
#endif /* !_MIPS_SETJMP_H_ */
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/* $OpenBSD: signal.h,v 1.8 2006/01/09 18:18:37 millert Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* Ralph Campbell.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)signal.h 8.1 (Berkeley) 6/10/93
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_SIGNAL_H_
|
||||
#define _MIPS_SIGNAL_H_
|
||||
|
||||
/* On Mips32, jmpbuf begins with optional 4-byte filler so that
|
||||
* all saved FP regs are aligned on 8-byte boundary, despite this whole
|
||||
* struct being mis-declared to users as an array of (4-byte) longs.
|
||||
* All the following offsets are then from the rounded-up base addr
|
||||
*/
|
||||
|
||||
/* Fields of same size on all MIPS abis: */
|
||||
#define SC_MAGIC (0*4) /* 4 bytes, identify jmpbuf */
|
||||
#define SC_MASK (1*4) /* 4 bytes, saved signal mask */
|
||||
#define SC_FPSR (2*4) /* 4 bytes, floating point control/status reg */
|
||||
/* filler2 (3*4) 4 bytes, pad to 8-byte boundary */
|
||||
|
||||
/* Registers that are 4-byte on mips32 o32, and 8-byte on mips64 n64 abi */
|
||||
#define SC_REGS_SAVED 12 /* ra,gp,sp,s0-s8 */
|
||||
#define SC_REGS (4*4) /* SC_REGS_SAVED*REGSZ bytes */
|
||||
|
||||
/* Floating pt registers are 8-bytes on all abis,
|
||||
* but the number of saved fp regs varies for o32/n32 versus n64 abis:
|
||||
*/
|
||||
|
||||
#ifdef __LP64__
|
||||
#define SC_FPREGS_SAVED 8 /* all fp regs f24,f25,f26,f27,f28,f29,f30,f31 */
|
||||
#else
|
||||
#define SC_FPREGS_SAVED 6 /* even fp regs f20,f22,f24,f26,f28,f30 */
|
||||
#endif
|
||||
|
||||
#define SC_FPREGS (SC_REGS + SC_REGS_SAVED*REGSZ) /* SC_FPREGS_SAVED*REGSZ_FP bytes */
|
||||
|
||||
#define SC_BYTES (SC_FPREGS + SC_FPREGS_SAVED*REGSZ_FP)
|
||||
#define SC_LONGS (SC_BYTES/REGSZ)
|
||||
|
||||
#ifdef __LP64__
|
||||
/* SC_LONGS is 22, so _JBLEN should be 22 or larger */
|
||||
#else
|
||||
/* SC_LONGS is 28, but must also allocate dynamic-roundup filler.
|
||||
so _JBLEN should be 29 or larger */
|
||||
#endif
|
||||
|
||||
#endif /* !_MIPS_SIGNAL_H_ */
|
||||
Loading…
Reference in a new issue