Merge "Move to arm-optimized-routines memset()." am: db681c0223
Original change: https://android-review.googlesource.com/c/platform/bionic/+/2307216 Change-Id: I60bcf6ed92653f6b8fa92021b715362821827cc9 Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
This commit is contained in:
Elliott Hughes
Automerger Merge Worker
commit
4bfa3e385d
5 changed files with 2 additions and 300 deletions
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@ -811,8 +811,8 @@ cc_library_static {
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arm64: {
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arm64: {
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cflags: ["-DHAVE_ASSEMBLER___MEMCPY_CHK"],
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cflags: ["-DHAVE_ASSEMBLER___MEMCPY_CHK"],
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srcs: [
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srcs: [
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"arch-arm64/generic/bionic/__memcpy_chk.S",
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"arch-arm64/string/__memcpy_chk.S",
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"arch-arm64/generic/bionic/__memset_chk.S",
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"arch-arm64/string/__memset_chk.S",
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],
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],
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},
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},
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},
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},
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@ -896,8 +896,6 @@ cc_library_static {
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},
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},
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arm64: {
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arm64: {
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srcs: [
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srcs: [
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"arch-arm64/generic/bionic/memset.S",
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"arch-arm64/bionic/__bionic_clone.S",
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"arch-arm64/bionic/__bionic_clone.S",
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"arch-arm64/bionic/_exit_with_stack_teardown.S",
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"arch-arm64/bionic/_exit_with_stack_teardown.S",
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"arch-arm64/bionic/setjmp.S",
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"arch-arm64/bionic/setjmp.S",
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@ -905,7 +903,6 @@ cc_library_static {
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"arch-arm64/bionic/vfork.S",
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"arch-arm64/bionic/vfork.S",
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],
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],
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exclude_srcs: [
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exclude_srcs: [
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"bionic/__memcpy_chk.cpp",
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"bionic/strchr.cpp",
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"bionic/strchr.cpp",
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"bionic/strchrnul.cpp",
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"bionic/strchrnul.cpp",
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"bionic/strnlen.c",
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"bionic/strnlen.c",
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55
libc/NOTICE
55
libc/NOTICE
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@ -4302,33 +4302,6 @@ THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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Copyright (c) 2012-2013, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
|
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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-------------------------------------------------------------------
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Copyright (c) 2012-2014 ARM Ltd
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Copyright (c) 2012-2014 ARM Ltd
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All rights reserved.
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All rights reserved.
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@ -4460,34 +4433,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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Copyright (c) 2015 ARM Ltd
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code must retain the above copyright
|
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
|
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. The name of the company may not be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-------------------------------------------------------------------
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Copyright (c) 2015 Joerg Sonnenberger <joerg@NetBSD.org>.
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Copyright (c) 2015 Joerg Sonnenberger <joerg@NetBSD.org>.
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All rights reserved.
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All rights reserved.
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@ -1,240 +0,0 @@
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/* Copyright (c) 2012-2013, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
|
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modification, are permitted provided that the following conditions are met:
|
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* Redistributions of source code must retain the above copyright
|
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notice, this list of conditions and the following disclaimer.
|
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* Redistributions in binary form must reproduce the above copyright
|
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notice, this list of conditions and the following disclaimer in the
|
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documentation and/or other materials provided with the distribution.
|
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* Neither the name of the Linaro nor the
|
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names of its contributors may be used to endorse or promote products
|
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/*
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* Copyright (c) 2015 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses
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*
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*/
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#include <private/bionic_asm.h>
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/* By default we assume that the DC instruction can be used to zero
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data blocks more efficiently. In some circumstances this might be
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unsafe, for example in an asymmetric multiprocessor environment with
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different DC clear lengths (neither the upper nor lower lengths are
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safe to use).
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If code may be run in a virtualized environment, then define
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MAYBE_VIRT. This will cause the code to cache the system register
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values rather than re-reading them each call. */
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define tmp1 x5
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#define tmp1w w5
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#define tmp2 x6
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#define tmp2w w6
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#define zva_len x7
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#define zva_lenw w7
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#define L(l) .L ## l
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ENTRY(memset)
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dup v0.16B, valw
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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mov val, v0.D[0]
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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nop
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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ret
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2: cbz count, 3f
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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3: ret
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/* Set 17..96 bytes. */
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L(set_medium):
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str q0, [dstin]
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tbnz count, 6, L(set96)
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str q0, [dstend, -16]
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tbz count, 5, 1f
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str q0, [dstin, 16]
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str q0, [dstend, -32]
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1: ret
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.p2align 4
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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str q0, [dstin, 16]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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nop
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L(set_long):
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and valw, valw, 255
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bic dst, dstin, 15
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str q0, [dstin]
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cmp count, 256
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ccmp valw, 0, 0, cs
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b.eq L(try_zva)
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L(no_zva):
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sub count, dstend, dst /* Count is 16 too large. */
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add dst, dst, 16
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sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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1: stp q0, q0, [dst], 64
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stp q0, q0, [dst, -32]
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L(tail64):
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subs count, count, 64
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b.hi 1b
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2: stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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L(try_zva):
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mrs tmp1, dczid_el0
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tbnz tmp1w, 4, L(no_zva)
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and tmp1w, tmp1w, 15
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cmp tmp1w, 4 /* ZVA size is 64 bytes. */
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b.ne L(zva_128)
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/* Write the first and last 64 byte aligned block using stp rather
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than using DC ZVA. This is faster on some cores.
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*/
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L(zva_64):
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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bic dst, dst, 63
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stp q0, q0, [dst, 64]
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stp q0, q0, [dst, 96]
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sub count, dstend, dst /* Count is now 128 too large. */
|
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sub count, count, 128+64+64 /* Adjust count and bias for loop. */
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add dst, dst, 128
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nop
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1: dc zva, dst
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add dst, dst, 64
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subs count, count, 64
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b.hi 1b
|
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stp q0, q0, [dst, 0]
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stp q0, q0, [dst, 32]
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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L(zva_128):
|
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cmp tmp1w, 5 /* ZVA size is 128 bytes. */
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b.ne L(zva_other)
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|
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]
|
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stp q0, q0, [dst, 96]
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bic dst, dst, 127
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sub count, dstend, dst /* Count is now 128 too large. */
|
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sub count, count, 128+128 /* Adjust count and bias for loop. */
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add dst, dst, 128
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1: dc zva, dst
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add dst, dst, 128
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subs count, count, 128
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b.hi 1b
|
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stp q0, q0, [dstend, -128]
|
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stp q0, q0, [dstend, -96]
|
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||||||
stp q0, q0, [dstend, -64]
|
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||||||
stp q0, q0, [dstend, -32]
|
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ret
|
|
||||||
|
|
||||||
L(zva_other):
|
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||||||
mov tmp2w, 4
|
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lsl zva_lenw, tmp2w, tmp1w
|
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||||||
add tmp1, zva_len, 64 /* Max alignment bytes written. */
|
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cmp count, tmp1
|
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||||||
blo L(no_zva)
|
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||||||
|
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sub tmp2, zva_len, 1
|
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||||||
add tmp1, dst, zva_len
|
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||||||
add dst, dst, 16
|
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||||||
subs count, tmp1, dst /* Actual alignment bytes to write. */
|
|
||||||
bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */
|
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||||||
beq 2f
|
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||||||
1: stp q0, q0, [dst], 64
|
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||||||
stp q0, q0, [dst, -32]
|
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||||||
subs count, count, 64
|
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||||||
b.hi 1b
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||||||
2: mov dst, tmp1
|
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||||||
sub count, dstend, tmp1 /* Remaining bytes to write. */
|
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||||||
subs count, count, zva_len
|
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b.lo 4f
|
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3: dc zva, dst
|
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||||||
add dst, dst, zva_len
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||||||
subs count, count, zva_len
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b.hs 3b
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4: add count, count, zva_len
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b L(tail64)
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||||||
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||||||
END(memset)
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||||||
|
|
||||||
NOTE_GNU_PROPERTY()
|
|
||||||
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