Clean up mips references in the headers.
Test: treehugger Change-Id: I1997af980b9e46c7c530f9e6cb1aa407b2d63d76
This commit is contained in:
parent
7482e240cf
commit
5ac438e5da
20 changed files with 26 additions and 434 deletions
25
libc/NOTICE
25
libc/NOTICE
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@ -3524,31 +3524,6 @@ POSSIBILITY OF SUCH DAMAGE.
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Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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SUCH DAMAGE.
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-------------------------------------------------------------------
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Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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@ -27,7 +27,6 @@
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#define __INTRODUCED_IN_64(api_level) __attribute__((annotate("introduced_in_64=" #api_level)))
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#define __INTRODUCED_IN_ARM(api_level) __attribute__((annotate("introduced_in_arm=" #api_level)))
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#define __INTRODUCED_IN_X86(api_level) __attribute__((annotate("introduced_in_x86=" #api_level)))
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#define __INTRODUCED_IN_MIPS(api_level)
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#define __VERSIONER_NO_GUARD __attribute__((annotate("versioner_no_guard")))
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#define __VERSIONER_FORTIFY_INLINE __attribute__((annotate("versioner_fortify_inline")))
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@ -41,7 +40,6 @@
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#define __INTRODUCED_IN_64(api_level)
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#define __INTRODUCED_IN_ARM(api_level)
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#define __INTRODUCED_IN_X86(api_level)
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#define __INTRODUCED_IN_MIPS(api_level)
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#define __VERSIONER_NO_GUARD
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#define __VERSIONER_FORTIFY_INLINE
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@ -26,15 +26,14 @@
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* SUCH DAMAGE.
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*/
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#ifndef _BITS_SIGNAL_TYPES_H_
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#define _BITS_SIGNAL_TYPES_H_
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#pragma once
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#include <limits.h>
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#include <sys/cdefs.h>
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#include <sys/types.h>
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/* For 64-bit (and mips), the kernel's struct sigaction doesn't match the
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* POSIX one, so we need to expose our own and translate behind the scenes.
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/* For 64-bit, the kernel's struct sigaction doesn't match the POSIX one,
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* so we need to expose our own and translate behind the scenes.
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* For 32-bit, we're stuck with the definitions we already shipped,
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* even though they contain a sigset_t that's too small. See sigaction64.
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*/
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@ -56,10 +55,10 @@ typedef int sig_atomic_t;
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typedef __sighandler_t sig_t; /* BSD compatibility. */
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typedef __sighandler_t sighandler_t; /* glibc compatibility. */
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/* sigset_t is already large enough on LP64 and mips, but other LP32's sigset_t
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/* sigset_t is already large enough on LP64, but LP32's sigset_t
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* is just `unsigned long`.
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*/
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#if defined(__LP64__) || defined(__mips__)
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#if defined(__LP64__)
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typedef sigset_t sigset64_t;
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#else
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typedef struct { unsigned long __bits[_KERNEL__NSIG/LONG_BIT]; } sigset64_t;
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@ -81,21 +80,6 @@ struct sigaction64 { __SIGACTION_BODY };
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#undef __SIGACTION_BODY
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#elif defined(__mips__)
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#define __SIGACTION_BODY \
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int sa_flags; \
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union { \
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sighandler_t sa_handler; \
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void (*sa_sigaction)(int, struct siginfo*, void*); \
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}; \
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sigset_t sa_mask; \
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struct sigaction { __SIGACTION_BODY };
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struct sigaction64 { __SIGACTION_BODY };
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#undef __SIGACTION_BODY
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#else
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#undef sa_handler
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@ -123,5 +107,3 @@ struct sigaction64 {
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};
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#endif
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#endif
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@ -53,8 +53,7 @@ int sched_rr_get_interval(pid_t __pid, struct timespec* __quantum);
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#if defined(__USE_GNU)
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int clone(int (*__fn)(void*), void* __child_stack, int __flags, void* __arg, ...)
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__INTRODUCED_IN_ARM(9) __INTRODUCED_IN_MIPS(12) __INTRODUCED_IN_X86(17);
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int clone(int (*__fn)(void*), void* __child_stack, int __flags, void* __arg, ...) __INTRODUCED_IN_ARM(9) __INTRODUCED_IN_X86(17);
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int unshare(int __flags) __INTRODUCED_IN(17);
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int sched_getcpu(void);
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int setns(int __fd, int __ns_type) __INTRODUCED_IN(21);
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@ -48,12 +48,6 @@
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#define _JBLEN 64
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#elif defined(__i386__)
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#define _JBLEN 10
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#elif defined(__mips__)
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#if defined(__LP64__)
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#define _JBLEN 25
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#else
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#define _JBLEN 157
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#endif
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#elif defined(__x86_64__)
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#define _JBLEN 11
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#endif
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@ -26,12 +26,8 @@
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* SUCH DAMAGE.
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*/
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#ifndef _SYS_CACHECTL_H
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#define _SYS_CACHECTL_H 1
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#pragma once
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#include <sys/cdefs.h>
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#ifdef __mips__
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#include <asm/cachectl.h>
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#endif
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#endif
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/* This header file is obsolete. */
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@ -46,13 +46,8 @@ __BEGIN_DECLS
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struct timespec;
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#ifdef __mips__
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#define SOCK_DGRAM 1
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#define SOCK_STREAM 2
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#else
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#define SOCK_STREAM 1
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#define SOCK_DGRAM 2
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#endif
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#define SOCK_RAW 3
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#define SOCK_RDM 4
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#define SOCK_SEQPACKET 5
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@ -36,7 +36,7 @@
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__BEGIN_DECLS
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#if defined(__aarch64__) || (defined(__mips__) && defined(__LP64__))
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#if defined(__aarch64__)
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#define __STAT64_BODY \
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dev_t st_dev; \
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ino_t st_ino; \
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@ -56,25 +56,6 @@ __BEGIN_DECLS
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unsigned int __unused4; \
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unsigned int __unused5; \
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#elif defined(__mips__) && !defined(__LP64__)
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#define __STAT64_BODY \
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unsigned int st_dev; \
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unsigned int __pad0[3]; \
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unsigned long long st_ino; \
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mode_t st_mode; \
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nlink_t st_nlink; \
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uid_t st_uid; \
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gid_t st_gid; \
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unsigned int st_rdev; \
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unsigned int __pad1[3]; \
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long long st_size; \
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struct timespec st_atim; \
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struct timespec st_mtim; \
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struct timespec st_ctim; \
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unsigned int st_blksize; \
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unsigned int __pad2; \
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unsigned long long st_blocks; \
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#elif defined(__x86_64__)
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#define __STAT64_BODY \
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dev_t st_dev; \
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@ -213,78 +213,6 @@ typedef struct ucontext {
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struct _libc_fpstate __fpregs_mem;
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} ucontext_t;
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#elif defined(__mips__)
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/* glibc doesn't have names for MIPS registers. */
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#define NGREG 32
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#define NFPREG 32
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typedef unsigned long long greg_t;
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typedef greg_t gregset_t[NGREG];
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typedef struct fpregset {
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union {
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double fp_dregs[NFPREG];
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struct {
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float _fp_fregs;
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unsigned _fp_pad;
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} fp_fregs[NFPREG];
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} fp_r;
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} fpregset_t;
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#ifdef __LP64__
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typedef struct {
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gregset_t gregs;
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fpregset_t fpregs;
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greg_t mdhi;
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greg_t hi1;
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greg_t hi2;
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greg_t hi3;
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greg_t mdlo;
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greg_t lo1;
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greg_t lo2;
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greg_t lo3;
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greg_t pc;
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uint32_t fpc_csr;
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uint32_t used_math;
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uint32_t dsp;
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uint32_t reserved;
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} mcontext_t;
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#else
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typedef struct {
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unsigned regmask;
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unsigned status;
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greg_t pc;
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gregset_t gregs;
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fpregset_t fpregs;
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unsigned fp_owned;
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unsigned fpc_csr;
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unsigned fpc_eir;
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unsigned used_math;
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unsigned dsp;
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greg_t mdhi;
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greg_t mdlo;
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unsigned long hi1;
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unsigned long lo1;
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unsigned long hi2;
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unsigned long lo2;
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unsigned long hi3;
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unsigned long lo3;
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} mcontext_t;
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#endif
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typedef struct ucontext {
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unsigned long uc_flags;
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struct ucontext* uc_link;
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stack_t uc_stack;
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mcontext_t uc_mcontext;
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union {
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sigset_t uc_sigmask;
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sigset64_t uc_sigmask64;
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};
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} ucontext_t;
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#elif defined(__x86_64__)
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enum {
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@ -172,22 +172,6 @@ struct user {
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unsigned long fault_address;
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};
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#elif defined(__mips__)
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struct user {
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unsigned long regs[180 / sizeof(unsigned long) + 64];
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size_t u_tsize;
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size_t u_dsize;
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size_t u_ssize;
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unsigned long start_code;
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unsigned long start_data;
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unsigned long start_stack;
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long int signal;
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void* u_ar0;
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unsigned long magic;
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char u_comm[32];
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};
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#elif defined(__arm__)
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struct user_fpregs {
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@ -39,7 +39,7 @@ __BEGIN_DECLS
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typedef struct { int __val[2]; } __fsid_t;
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typedef __fsid_t fsid_t;
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#if defined(__aarch64__) || defined(__x86_64__)
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#if defined(__LP64__)
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#define __STATFS64_BODY \
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uint64_t f_type; \
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uint64_t f_bsize; \
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uint64_t f_flags; \
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uint64_t f_spare[4]; \
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#elif defined(__mips__) && defined(__LP64__)
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/* 64-bit MIPS. */
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#define __STATFS64_BODY \
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uint64_t f_type; \
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uint64_t f_bsize; \
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uint64_t f_frsize; /* Fragment size - unsupported. */ \
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uint64_t f_blocks; \
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uint64_t f_bfree; \
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uint64_t f_files; \
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uint64_t f_ffree; \
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uint64_t f_bavail; \
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fsid_t f_fsid; \
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uint64_t f_namelen; \
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uint64_t f_flags; \
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uint64_t f_spare[5]; \
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#elif defined(__mips__)
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/* 32-bit MIPS (corresponds to the kernel's statfs64 type). */
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#define __STATFS64_BODY \
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uint32_t f_type; \
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uint32_t f_bsize; \
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uint32_t f_frsize; \
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uint32_t __pad; \
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uint64_t f_blocks; \
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uint64_t f_bfree; \
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uint64_t f_files; \
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uint64_t f_ffree; \
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uint64_t f_bavail; \
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fsid_t f_fsid; \
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uint32_t f_namelen; \
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uint32_t f_flags; \
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uint32_t f_spare[5]; \
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#else
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/* 32-bit ARM or x86 (corresponds to the kernel's statfs64 type). */
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#define __STATFS64_BODY \
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@ -294,7 +294,7 @@ long syscall(long __number, ...);
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int daemon(int __no_chdir, int __no_close);
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#if defined(__arm__) || (defined(__mips__) && !defined(__LP64__))
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#if defined(__arm__)
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int cacheflush(long __addr, long __nbytes, long __cache);
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/* __attribute__((deprecated("use __builtin___clear_cache instead"))); */
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#endif
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@ -57,8 +57,6 @@ static inline T* align_up(T* p, size_t align) {
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#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined \%eip")
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#elif defined(__x86_64__)
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#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined \%rip")
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#elif defined (__mips__)
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#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined $ra")
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#endif
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// The arraysize(arr) macro returns the # of elements in an array arr.
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@ -32,15 +32,6 @@
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# define __get_tls() ({ void** __val; __asm__("mrs %0, tpidr_el0" : "=r"(__val)); __val; })
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#elif defined(__arm__)
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# define __get_tls() ({ void** __val; __asm__("mrc p15, 0, %0, c13, c0, 3" : "=r"(__val)); __val; })
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#elif defined(__mips__)
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# define __get_tls() \
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/* On mips32r1, this goes via a kernel illegal instruction trap that's optimized for v1. */ \
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({ register void** __val asm("v1"); \
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__asm__(".set push\n" \
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".set mips32r2\n" \
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"rdhwr %0,$29\n" \
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".set pop\n" : "=r"(__val)); \
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__val; })
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#elif defined(__i386__)
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# define __get_tls() ({ void** __val; __asm__("movl %%gs:0, %0" : "=r"(__val)); __val; })
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#elif defined(__x86_64__)
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@ -42,8 +42,6 @@
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#include <private/bionic_asm_arm.h>
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#elif defined(__i386__)
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#include <private/bionic_asm_x86.h>
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#elif defined(__mips__)
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#include <private/bionic_asm_mips.h>
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#elif defined(__x86_64__)
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#include <private/bionic_asm_x86_64.h>
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#endif
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@ -1,187 +0,0 @@
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/* $OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */
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/*
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* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
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*
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*/
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#pragma once
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#define __bionic_asm_align 16
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#undef __bionic_asm_custom_entry
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#undef __bionic_asm_custom_end
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#define __bionic_asm_custom_entry(f) .ent f
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#define __bionic_asm_custom_end(f) .end f
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#define _MIPS_ISA_MIPS1 1 /* R2000/R3000 */
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#define _MIPS_ISA_MIPS2 2 /* R4000/R6000 */
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#define _MIPS_ISA_MIPS3 3 /* R4000 */
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#define _MIPS_ISA_MIPS4 4 /* TFP (R1x000) */
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#define _MIPS_ISA_MIPS5 5
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#define _MIPS_ISA_MIPS32 6
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#define _MIPS_ISA_MIPS64 7
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#if !defined(ABICALLS) && !defined(_NO_ABICALLS)
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#define ABICALLS .abicalls
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#endif
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#if defined(ABICALLS) && !defined(_KERNEL)
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ABICALLS
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#endif
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/*
|
||||
* Define how to access unaligned data word
|
||||
*/
|
||||
#define LWLO lwl
|
||||
#define LWHI lwr
|
||||
#define SWLO swl
|
||||
#define SWHI swr
|
||||
#define LDLO ldl
|
||||
#define LDHI ldr
|
||||
#define SDLO sdl
|
||||
#define SDHI sdr
|
||||
|
||||
/*
|
||||
* Define programming environment for ABI.
|
||||
*/
|
||||
#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE)
|
||||
|
||||
#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)
|
||||
#define NARGSAVE 4
|
||||
|
||||
#define SETUP_GP \
|
||||
.set noreorder; \
|
||||
.cpload $t9; \
|
||||
.set reorder;
|
||||
|
||||
#define SAVE_GP(x) \
|
||||
.cprestore x
|
||||
|
||||
#define SETUP_GP64(gpoff, name)
|
||||
#define RESTORE_GP64
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
|
||||
#define NARGSAVE 0
|
||||
|
||||
#define SETUP_GP
|
||||
#define SAVE_GP(x)
|
||||
#define SETUP_GP64(gpoff, name) \
|
||||
.cpsetup $t9, gpoff, name
|
||||
#define RESTORE_GP64 \
|
||||
.cpreturn
|
||||
#endif
|
||||
|
||||
#define MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31))
|
||||
|
||||
#else /* defined(ABICALLS) && !defined(_KERNEL) */
|
||||
|
||||
#define NARGSAVE 4
|
||||
#define SETUP_GP
|
||||
#define SAVE_GP(x)
|
||||
|
||||
#define ALIGNSZ 16 /* Stack layout alignment */
|
||||
#define FRAMESZ(sz) (((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1))
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Basic register operations based on selected ISA
|
||||
*/
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS32)
|
||||
#define REGSZ 4 /* 32 bit mode register size */
|
||||
#define LOGREGSZ 2 /* log rsize */
|
||||
#define REG_S sw
|
||||
#define REG_L lw
|
||||
#define CF_SZ 24 /* Call frame size */
|
||||
#define CF_ARGSZ 16 /* Call frame arg size */
|
||||
#define CF_RA_OFFS 20 /* Call ra save offset */
|
||||
#endif
|
||||
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS64)
|
||||
#define REGSZ 8 /* 64 bit mode register size */
|
||||
#define LOGREGSZ 3 /* log rsize */
|
||||
#define REG_S sd
|
||||
#define REG_L ld
|
||||
#define CF_SZ 48 /* Call frame size (multiple of ALIGNSZ) */
|
||||
#define CF_ARGSZ 32 /* Call frame arg size */
|
||||
#define CF_RA_OFFS 40 /* Call ra save offset */
|
||||
#endif
|
||||
|
||||
#define REGSZ_FP 8 /* 64 bit FP register size */
|
||||
|
||||
#ifndef __LP64__
|
||||
#define PTR_L lw
|
||||
#define PTR_S sw
|
||||
#define PTR_SUB sub
|
||||
#define PTR_ADD add
|
||||
#define PTR_SUBU subu
|
||||
#define PTR_ADDU addu
|
||||
#define LI li
|
||||
#define LA la
|
||||
#define PTR_SLL sll
|
||||
#define PTR_SRL srl
|
||||
#define PTR_VAL .word
|
||||
#else
|
||||
#define PTR_L ld
|
||||
#define PTR_S sd
|
||||
#define PTR_ADD dadd
|
||||
#define PTR_SUB dsub
|
||||
#define PTR_SUBU dsubu
|
||||
#define PTR_ADDU daddu
|
||||
#define LI dli
|
||||
#define LA dla
|
||||
#define PTR_SLL dsll
|
||||
#define PTR_SRL dsrl
|
||||
#define PTR_VAL .dword
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LEAF(x, fsize)
|
||||
*
|
||||
* Declare a leaf routine.
|
||||
*/
|
||||
#define LEAF(x, fsize) \
|
||||
.align 3; \
|
||||
.globl x; \
|
||||
.ent x, 0; \
|
||||
x: ; \
|
||||
.cfi_startproc; \
|
||||
.frame $sp, fsize, $ra; \
|
||||
SETUP_GP \
|
||||
|
||||
/*
|
||||
* NON_LEAF(x)
|
||||
*
|
||||
* Declare a non-leaf routine (a routine that makes other C calls).
|
||||
*/
|
||||
#define NON_LEAF(x, fsize, retpc) \
|
||||
.align 3; \
|
||||
.globl x; \
|
||||
.ent x, 0; \
|
||||
x: ; \
|
||||
.cfi_startproc; \
|
||||
.frame $sp, fsize, retpc; \
|
||||
SETUP_GP \
|
|
@ -26,20 +26,18 @@
|
|||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PRIVATE_SSP_H
|
||||
#define _PRIVATE_SSP_H
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
/* GCC uses this on ARM and MIPS; we use it on x86 to set the guard in TLS. */
|
||||
// The compiler uses this if it's not using TLS.
|
||||
// Currently that's on arm32 and on x86 before API 17.
|
||||
extern uintptr_t __stack_chk_guard;
|
||||
|
||||
/* GCC calls this if a stack guard check fails. */
|
||||
// The compiler calls this if a stack guard check fails.
|
||||
extern void __stack_chk_fail();
|
||||
|
||||
__END_DECLS
|
||||
|
||||
#endif
|
||||
|
|
|
@ -3,5 +3,5 @@
|
|||
|
||||
CRTBEGIN {
|
||||
global:
|
||||
atexit; # arm64 x86 x86_64 mips mips64
|
||||
atexit; # arm64 x86 x86_64
|
||||
};
|
||||
|
|
|
@ -54,26 +54,23 @@ int multiple_archs() __INTRODUCED_IN(14);
|
|||
|
||||
// __INTRODUCED_IN_64(21) should be ignored.
|
||||
|
||||
#if (defined(__LP64__)) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13)
|
||||
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
|
||||
__INTRODUCED_IN_64(21);
|
||||
#endif /* (defined(__LP64__)) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13) */
|
||||
#if (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__))
|
||||
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(21);
|
||||
#endif /* (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__)) */
|
||||
|
||||
|
||||
|
||||
#if (defined(__LP64__) && __ANDROID_API__ >= 22) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13)
|
||||
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
|
||||
__INTRODUCED_IN_64(22);
|
||||
#endif /* (defined(__LP64__) && __ANDROID_API__ >= 22) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13) */
|
||||
#if (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__) && __ANDROID_API__ >= 22)
|
||||
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(22);
|
||||
#endif /* (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__) && __ANDROID_API__ >= 22) */
|
||||
|
||||
|
||||
|
||||
#if (!defined(__LP64__) && __ANDROID_API__ >= 12) || (defined(__LP64__))
|
||||
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12) __INTRODUCED_IN_MIPS(12);
|
||||
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12);
|
||||
#endif /* (!defined(__LP64__) && __ANDROID_API__ >= 12) || (defined(__LP64__)) */
|
||||
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -37,13 +37,11 @@ int multiple_archs() __INTRODUCED_IN(14);
|
|||
#endif
|
||||
|
||||
// __INTRODUCED_IN_64(21) should be ignored.
|
||||
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
|
||||
__INTRODUCED_IN_64(21);
|
||||
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(21);
|
||||
|
||||
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
|
||||
__INTRODUCED_IN_64(22);
|
||||
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(22);
|
||||
|
||||
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12) __INTRODUCED_IN_MIPS(12);
|
||||
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue