Clean up mips references in the headers.

Test: treehugger
Change-Id: I1997af980b9e46c7c530f9e6cb1aa407b2d63d76
This commit is contained in:
Elliott Hughes 2020-02-13 15:56:31 -08:00
parent 7482e240cf
commit 5ac438e5da
20 changed files with 26 additions and 434 deletions

View file

@ -3524,31 +3524,6 @@ POSSIBILITY OF SUCH DAMAGE.
Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
-------------------------------------------------------------------
Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:

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@ -27,7 +27,6 @@
#define __INTRODUCED_IN_64(api_level) __attribute__((annotate("introduced_in_64=" #api_level)))
#define __INTRODUCED_IN_ARM(api_level) __attribute__((annotate("introduced_in_arm=" #api_level)))
#define __INTRODUCED_IN_X86(api_level) __attribute__((annotate("introduced_in_x86=" #api_level)))
#define __INTRODUCED_IN_MIPS(api_level)
#define __VERSIONER_NO_GUARD __attribute__((annotate("versioner_no_guard")))
#define __VERSIONER_FORTIFY_INLINE __attribute__((annotate("versioner_fortify_inline")))
@ -41,7 +40,6 @@
#define __INTRODUCED_IN_64(api_level)
#define __INTRODUCED_IN_ARM(api_level)
#define __INTRODUCED_IN_X86(api_level)
#define __INTRODUCED_IN_MIPS(api_level)
#define __VERSIONER_NO_GUARD
#define __VERSIONER_FORTIFY_INLINE

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@ -26,15 +26,14 @@
* SUCH DAMAGE.
*/
#ifndef _BITS_SIGNAL_TYPES_H_
#define _BITS_SIGNAL_TYPES_H_
#pragma once
#include <limits.h>
#include <sys/cdefs.h>
#include <sys/types.h>
/* For 64-bit (and mips), the kernel's struct sigaction doesn't match the
* POSIX one, so we need to expose our own and translate behind the scenes.
/* For 64-bit, the kernel's struct sigaction doesn't match the POSIX one,
* so we need to expose our own and translate behind the scenes.
* For 32-bit, we're stuck with the definitions we already shipped,
* even though they contain a sigset_t that's too small. See sigaction64.
*/
@ -56,10 +55,10 @@ typedef int sig_atomic_t;
typedef __sighandler_t sig_t; /* BSD compatibility. */
typedef __sighandler_t sighandler_t; /* glibc compatibility. */
/* sigset_t is already large enough on LP64 and mips, but other LP32's sigset_t
/* sigset_t is already large enough on LP64, but LP32's sigset_t
* is just `unsigned long`.
*/
#if defined(__LP64__) || defined(__mips__)
#if defined(__LP64__)
typedef sigset_t sigset64_t;
#else
typedef struct { unsigned long __bits[_KERNEL__NSIG/LONG_BIT]; } sigset64_t;
@ -81,21 +80,6 @@ struct sigaction64 { __SIGACTION_BODY };
#undef __SIGACTION_BODY
#elif defined(__mips__)
#define __SIGACTION_BODY \
int sa_flags; \
union { \
sighandler_t sa_handler; \
void (*sa_sigaction)(int, struct siginfo*, void*); \
}; \
sigset_t sa_mask; \
struct sigaction { __SIGACTION_BODY };
struct sigaction64 { __SIGACTION_BODY };
#undef __SIGACTION_BODY
#else
#undef sa_handler
@ -123,5 +107,3 @@ struct sigaction64 {
};
#endif
#endif

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@ -53,8 +53,7 @@ int sched_rr_get_interval(pid_t __pid, struct timespec* __quantum);
#if defined(__USE_GNU)
int clone(int (*__fn)(void*), void* __child_stack, int __flags, void* __arg, ...)
__INTRODUCED_IN_ARM(9) __INTRODUCED_IN_MIPS(12) __INTRODUCED_IN_X86(17);
int clone(int (*__fn)(void*), void* __child_stack, int __flags, void* __arg, ...) __INTRODUCED_IN_ARM(9) __INTRODUCED_IN_X86(17);
int unshare(int __flags) __INTRODUCED_IN(17);
int sched_getcpu(void);
int setns(int __fd, int __ns_type) __INTRODUCED_IN(21);

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@ -48,12 +48,6 @@
#define _JBLEN 64
#elif defined(__i386__)
#define _JBLEN 10
#elif defined(__mips__)
#if defined(__LP64__)
#define _JBLEN 25
#else
#define _JBLEN 157
#endif
#elif defined(__x86_64__)
#define _JBLEN 11
#endif

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@ -26,12 +26,8 @@
* SUCH DAMAGE.
*/
#ifndef _SYS_CACHECTL_H
#define _SYS_CACHECTL_H 1
#pragma once
#include <sys/cdefs.h>
#ifdef __mips__
#include <asm/cachectl.h>
#endif
#endif
/* This header file is obsolete. */

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@ -46,13 +46,8 @@ __BEGIN_DECLS
struct timespec;
#ifdef __mips__
#define SOCK_DGRAM 1
#define SOCK_STREAM 2
#else
#define SOCK_STREAM 1
#define SOCK_DGRAM 2
#endif
#define SOCK_RAW 3
#define SOCK_RDM 4
#define SOCK_SEQPACKET 5

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@ -36,7 +36,7 @@
__BEGIN_DECLS
#if defined(__aarch64__) || (defined(__mips__) && defined(__LP64__))
#if defined(__aarch64__)
#define __STAT64_BODY \
dev_t st_dev; \
ino_t st_ino; \
@ -56,25 +56,6 @@ __BEGIN_DECLS
unsigned int __unused4; \
unsigned int __unused5; \
#elif defined(__mips__) && !defined(__LP64__)
#define __STAT64_BODY \
unsigned int st_dev; \
unsigned int __pad0[3]; \
unsigned long long st_ino; \
mode_t st_mode; \
nlink_t st_nlink; \
uid_t st_uid; \
gid_t st_gid; \
unsigned int st_rdev; \
unsigned int __pad1[3]; \
long long st_size; \
struct timespec st_atim; \
struct timespec st_mtim; \
struct timespec st_ctim; \
unsigned int st_blksize; \
unsigned int __pad2; \
unsigned long long st_blocks; \
#elif defined(__x86_64__)
#define __STAT64_BODY \
dev_t st_dev; \

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@ -213,78 +213,6 @@ typedef struct ucontext {
struct _libc_fpstate __fpregs_mem;
} ucontext_t;
#elif defined(__mips__)
/* glibc doesn't have names for MIPS registers. */
#define NGREG 32
#define NFPREG 32
typedef unsigned long long greg_t;
typedef greg_t gregset_t[NGREG];
typedef struct fpregset {
union {
double fp_dregs[NFPREG];
struct {
float _fp_fregs;
unsigned _fp_pad;
} fp_fregs[NFPREG];
} fp_r;
} fpregset_t;
#ifdef __LP64__
typedef struct {
gregset_t gregs;
fpregset_t fpregs;
greg_t mdhi;
greg_t hi1;
greg_t hi2;
greg_t hi3;
greg_t mdlo;
greg_t lo1;
greg_t lo2;
greg_t lo3;
greg_t pc;
uint32_t fpc_csr;
uint32_t used_math;
uint32_t dsp;
uint32_t reserved;
} mcontext_t;
#else
typedef struct {
unsigned regmask;
unsigned status;
greg_t pc;
gregset_t gregs;
fpregset_t fpregs;
unsigned fp_owned;
unsigned fpc_csr;
unsigned fpc_eir;
unsigned used_math;
unsigned dsp;
greg_t mdhi;
greg_t mdlo;
unsigned long hi1;
unsigned long lo1;
unsigned long hi2;
unsigned long lo2;
unsigned long hi3;
unsigned long lo3;
} mcontext_t;
#endif
typedef struct ucontext {
unsigned long uc_flags;
struct ucontext* uc_link;
stack_t uc_stack;
mcontext_t uc_mcontext;
union {
sigset_t uc_sigmask;
sigset64_t uc_sigmask64;
};
} ucontext_t;
#elif defined(__x86_64__)
enum {

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@ -172,22 +172,6 @@ struct user {
unsigned long fault_address;
};
#elif defined(__mips__)
struct user {
unsigned long regs[180 / sizeof(unsigned long) + 64];
size_t u_tsize;
size_t u_dsize;
size_t u_ssize;
unsigned long start_code;
unsigned long start_data;
unsigned long start_stack;
long int signal;
void* u_ar0;
unsigned long magic;
char u_comm[32];
};
#elif defined(__arm__)
struct user_fpregs {

View file

@ -39,7 +39,7 @@ __BEGIN_DECLS
typedef struct { int __val[2]; } __fsid_t;
typedef __fsid_t fsid_t;
#if defined(__aarch64__) || defined(__x86_64__)
#if defined(__LP64__)
#define __STATFS64_BODY \
uint64_t f_type; \
uint64_t f_bsize; \
@ -54,39 +54,6 @@ typedef __fsid_t fsid_t;
uint64_t f_flags; \
uint64_t f_spare[4]; \
#elif defined(__mips__) && defined(__LP64__)
/* 64-bit MIPS. */
#define __STATFS64_BODY \
uint64_t f_type; \
uint64_t f_bsize; \
uint64_t f_frsize; /* Fragment size - unsupported. */ \
uint64_t f_blocks; \
uint64_t f_bfree; \
uint64_t f_files; \
uint64_t f_ffree; \
uint64_t f_bavail; \
fsid_t f_fsid; \
uint64_t f_namelen; \
uint64_t f_flags; \
uint64_t f_spare[5]; \
#elif defined(__mips__)
/* 32-bit MIPS (corresponds to the kernel's statfs64 type). */
#define __STATFS64_BODY \
uint32_t f_type; \
uint32_t f_bsize; \
uint32_t f_frsize; \
uint32_t __pad; \
uint64_t f_blocks; \
uint64_t f_bfree; \
uint64_t f_files; \
uint64_t f_ffree; \
uint64_t f_bavail; \
fsid_t f_fsid; \
uint32_t f_namelen; \
uint32_t f_flags; \
uint32_t f_spare[5]; \
#else
/* 32-bit ARM or x86 (corresponds to the kernel's statfs64 type). */
#define __STATFS64_BODY \

View file

@ -294,7 +294,7 @@ long syscall(long __number, ...);
int daemon(int __no_chdir, int __no_close);
#if defined(__arm__) || (defined(__mips__) && !defined(__LP64__))
#if defined(__arm__)
int cacheflush(long __addr, long __nbytes, long __cache);
/* __attribute__((deprecated("use __builtin___clear_cache instead"))); */
#endif

View file

@ -57,8 +57,6 @@ static inline T* align_up(T* p, size_t align) {
#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined \%eip")
#elif defined(__x86_64__)
#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined \%rip")
#elif defined (__mips__)
#define BIONIC_STOP_UNWIND asm volatile(".cfi_undefined $ra")
#endif
// The arraysize(arr) macro returns the # of elements in an array arr.

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@ -32,15 +32,6 @@
# define __get_tls() ({ void** __val; __asm__("mrs %0, tpidr_el0" : "=r"(__val)); __val; })
#elif defined(__arm__)
# define __get_tls() ({ void** __val; __asm__("mrc p15, 0, %0, c13, c0, 3" : "=r"(__val)); __val; })
#elif defined(__mips__)
# define __get_tls() \
/* On mips32r1, this goes via a kernel illegal instruction trap that's optimized for v1. */ \
({ register void** __val asm("v1"); \
__asm__(".set push\n" \
".set mips32r2\n" \
"rdhwr %0,$29\n" \
".set pop\n" : "=r"(__val)); \
__val; })
#elif defined(__i386__)
# define __get_tls() ({ void** __val; __asm__("movl %%gs:0, %0" : "=r"(__val)); __val; })
#elif defined(__x86_64__)

View file

@ -42,8 +42,6 @@
#include <private/bionic_asm_arm.h>
#elif defined(__i386__)
#include <private/bionic_asm_x86.h>
#elif defined(__mips__)
#include <private/bionic_asm_mips.h>
#elif defined(__x86_64__)
#include <private/bionic_asm_x86_64.h>
#endif

View file

@ -1,187 +0,0 @@
/* $OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */
/*
* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#pragma once
#define __bionic_asm_align 16
#undef __bionic_asm_custom_entry
#undef __bionic_asm_custom_end
#define __bionic_asm_custom_entry(f) .ent f
#define __bionic_asm_custom_end(f) .end f
#define _MIPS_ISA_MIPS1 1 /* R2000/R3000 */
#define _MIPS_ISA_MIPS2 2 /* R4000/R6000 */
#define _MIPS_ISA_MIPS3 3 /* R4000 */
#define _MIPS_ISA_MIPS4 4 /* TFP (R1x000) */
#define _MIPS_ISA_MIPS5 5
#define _MIPS_ISA_MIPS32 6
#define _MIPS_ISA_MIPS64 7
#if !defined(ABICALLS) && !defined(_NO_ABICALLS)
#define ABICALLS .abicalls
#endif
#if defined(ABICALLS) && !defined(_KERNEL)
ABICALLS
#endif
/*
* Define how to access unaligned data word
*/
#define LWLO lwl
#define LWHI lwr
#define SWLO swl
#define SWHI swr
#define LDLO ldl
#define LDHI ldr
#define SDLO sdl
#define SDHI sdr
/*
* Define programming environment for ABI.
*/
#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE)
#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)
#define NARGSAVE 4
#define SETUP_GP \
.set noreorder; \
.cpload $t9; \
.set reorder;
#define SAVE_GP(x) \
.cprestore x
#define SETUP_GP64(gpoff, name)
#define RESTORE_GP64
#endif
#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
#define NARGSAVE 0
#define SETUP_GP
#define SAVE_GP(x)
#define SETUP_GP64(gpoff, name) \
.cpsetup $t9, gpoff, name
#define RESTORE_GP64 \
.cpreturn
#endif
#define MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31))
#else /* defined(ABICALLS) && !defined(_KERNEL) */
#define NARGSAVE 4
#define SETUP_GP
#define SAVE_GP(x)
#define ALIGNSZ 16 /* Stack layout alignment */
#define FRAMESZ(sz) (((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1))
#endif
/*
* Basic register operations based on selected ISA
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS32)
#define REGSZ 4 /* 32 bit mode register size */
#define LOGREGSZ 2 /* log rsize */
#define REG_S sw
#define REG_L lw
#define CF_SZ 24 /* Call frame size */
#define CF_ARGSZ 16 /* Call frame arg size */
#define CF_RA_OFFS 20 /* Call ra save offset */
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS64)
#define REGSZ 8 /* 64 bit mode register size */
#define LOGREGSZ 3 /* log rsize */
#define REG_S sd
#define REG_L ld
#define CF_SZ 48 /* Call frame size (multiple of ALIGNSZ) */
#define CF_ARGSZ 32 /* Call frame arg size */
#define CF_RA_OFFS 40 /* Call ra save offset */
#endif
#define REGSZ_FP 8 /* 64 bit FP register size */
#ifndef __LP64__
#define PTR_L lw
#define PTR_S sw
#define PTR_SUB sub
#define PTR_ADD add
#define PTR_SUBU subu
#define PTR_ADDU addu
#define LI li
#define LA la
#define PTR_SLL sll
#define PTR_SRL srl
#define PTR_VAL .word
#else
#define PTR_L ld
#define PTR_S sd
#define PTR_ADD dadd
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_ADDU daddu
#define LI dli
#define LA dla
#define PTR_SLL dsll
#define PTR_SRL dsrl
#define PTR_VAL .dword
#endif
/*
* LEAF(x, fsize)
*
* Declare a leaf routine.
*/
#define LEAF(x, fsize) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.cfi_startproc; \
.frame $sp, fsize, $ra; \
SETUP_GP \
/*
* NON_LEAF(x)
*
* Declare a non-leaf routine (a routine that makes other C calls).
*/
#define NON_LEAF(x, fsize, retpc) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.cfi_startproc; \
.frame $sp, fsize, retpc; \
SETUP_GP \

View file

@ -26,20 +26,18 @@
* SUCH DAMAGE.
*/
#ifndef _PRIVATE_SSP_H
#define _PRIVATE_SSP_H
#pragma once
#include <stdint.h>
#include <sys/cdefs.h>
__BEGIN_DECLS
/* GCC uses this on ARM and MIPS; we use it on x86 to set the guard in TLS. */
// The compiler uses this if it's not using TLS.
// Currently that's on arm32 and on x86 before API 17.
extern uintptr_t __stack_chk_guard;
/* GCC calls this if a stack guard check fails. */
// The compiler calls this if a stack guard check fails.
extern void __stack_chk_fail();
__END_DECLS
#endif

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@ -3,5 +3,5 @@
CRTBEGIN {
global:
atexit; # arm64 x86 x86_64 mips mips64
atexit; # arm64 x86 x86_64
};

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@ -54,26 +54,23 @@ int multiple_archs() __INTRODUCED_IN(14);
// __INTRODUCED_IN_64(21) should be ignored.
#if (defined(__LP64__)) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13)
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
__INTRODUCED_IN_64(21);
#endif /* (defined(__LP64__)) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13) */
#if (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__))
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(21);
#endif /* (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__)) */
#if (defined(__LP64__) && __ANDROID_API__ >= 22) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13)
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
__INTRODUCED_IN_64(22);
#endif /* (defined(__LP64__) && __ANDROID_API__ >= 22) || (defined(__arm__) && __ANDROID_API__ >= 13) || (defined(__mips__) && !defined(__LP64__) && __ANDROID_API__ >= 14) || (defined(__i386__) && __ANDROID_API__ >= 13) */
#if (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__) && __ANDROID_API__ >= 22)
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(22);
#endif /* (!defined(__LP64__) && __ANDROID_API__ >= 13) || (defined(__LP64__) && __ANDROID_API__ >= 22) */
#if (!defined(__LP64__) && __ANDROID_API__ >= 12) || (defined(__LP64__))
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12) __INTRODUCED_IN_MIPS(12);
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12);
#endif /* (!defined(__LP64__) && __ANDROID_API__ >= 12) || (defined(__LP64__)) */
#if defined(__cplusplus)
}
#endif

View file

@ -37,13 +37,11 @@ int multiple_archs() __INTRODUCED_IN(14);
#endif
// __INTRODUCED_IN_64(21) should be ignored.
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
__INTRODUCED_IN_64(21);
int multiple_introduced_1() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(21);
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_MIPS(14) __INTRODUCED_IN_X86(13)
__INTRODUCED_IN_64(22);
int multiple_introduced_2() __INTRODUCED_IN_ARM(13) __INTRODUCED_IN_X86(13) __INTRODUCED_IN_64(22);
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12) __INTRODUCED_IN_MIPS(12);
int group_lp32() __INTRODUCED_IN_ARM(12) __INTRODUCED_IN_X86(12);
#if defined(__cplusplus)
}