Add optimized stpcpy.
Change-Id: Ifed38f92a54fef4488fd0ed26a1569059a054574
This commit is contained in:
Christopher Ferris
parent
2e249c2e7a
commit
753eb7f07e
7 changed files with 277 additions and 167 deletions
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@ -11,7 +11,6 @@ libc_common_src_files_arm64 := \
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upstream-freebsd/lib/libc/string/wcslen.c \
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upstream-freebsd/lib/libc/string/wcsrchr.c \
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upstream-freebsd/lib/libc/string/wmemcmp.c \
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upstream-openbsd/lib/libc/string/stpcpy.c \
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upstream-openbsd/lib/libc/string/stpncpy.c \
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upstream-openbsd/lib/libc/string/strcat.c \
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upstream-openbsd/lib/libc/string/strlcat.c \
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@ -3,6 +3,7 @@ libc_bionic_src_files_arm64 += \
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arch-arm64/denver64/bionic/memcpy.S \
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arch-arm64/generic/bionic/memmove.S \
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arch-arm64/denver64/bionic/memset.S \
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arch-arm64/generic/bionic/stpcpy.S \
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arch-arm64/generic/bionic/strchr.S \
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arch-arm64/generic/bionic/strcmp.S \
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arch-arm64/generic/bionic/strcpy.S \
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@ -2,6 +2,7 @@ libc_bionic_src_files_arm64 += \
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arch-arm64/generic/bionic/memcmp.S \
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arch-arm64/generic/bionic/memmove.S \
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arch-arm64/generic/bionic/memset.S \
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arch-arm64/generic/bionic/stpcpy.S \
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arch-arm64/generic/bionic/strchr.S \
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arch-arm64/generic/bionic/strcmp.S \
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arch-arm64/generic/bionic/strcpy.S \
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29
libc/arch-arm64/generic/bionic/stpcpy.S
Normal file
29
libc/arch-arm64/generic/bionic/stpcpy.S
Normal file
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@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2014 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define STPCPY
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#include "string_copy.S"
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@ -25,169 +25,5 @@
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Copyright (c) 2014, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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*/
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#include <private/bionic_asm.h>
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/* Arguments and results. */
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#define dstin x0
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#define src x1
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/* Locals and temporaries. */
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#define dst x2
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#define data1 x3
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#define data1_w w3
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#define data2 x4
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#define data2_w w4
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#define has_nul1 x5
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#define has_nul1_w w5
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#define has_nul2 x6
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#define tmp1 x7
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#define tmp2 x8
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#define tmp3 x9
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#define tmp4 x10
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#define zeroones x11
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#define zeroones_w w11
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#define pos x12
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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ENTRY(strcpy)
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mov zeroones, #REP8_01
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mov dst, dstin
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ands tmp1, src, #15
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b.ne .Lmisaligned
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// NUL detection works on the principle that (X - 1) & (~X) & 0x80
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// (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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// can be done in parallel across the entire word.
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// The inner loop deals with two Dwords at a time. This has a
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// slightly higher start-up cost, but we should win quite quickly,
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// especially on cores with a high number of issue slots per
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// cycle, as we get much better parallelism out of the operations.
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.Lloop:
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ldp data1, data2, [src], #16
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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bic has_nul1, tmp1, tmp2
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cbnz has_nul1, .Lnul_in_data1
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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bic has_nul2, tmp3, tmp4
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cbnz has_nul2, .Lnul_in_data2
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// No NUL in either register, copy it in a single instruction.
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stp data1, data2, [dst], #16
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b .Lloop
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.Lnul_in_data1:
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rev has_nul1, has_nul1
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clz pos, has_nul1
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add tmp1, pos, #0x8
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tbz tmp1, #6, 1f
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str data1, [dst]
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ret
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1:
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tbz tmp1, #5, 1f
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str data1_w, [dst], #4
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lsr data1, data1, #32
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1:
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tbz tmp1, #4, 1f
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strh data1_w, [dst], #2
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lsr data1, data1, #16
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1:
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tbz tmp1, #3, 1f
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strb data1_w, [dst]
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1:
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ret
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.Lnul_in_data2:
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str data1, [dst], #8
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rev has_nul2, has_nul2
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clz pos, has_nul2
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add tmp1, pos, #0x8
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tbz tmp1, #6, 1f
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str data2, [dst]
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ret
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1:
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tbz tmp1, #5, 1f
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str data2_w, [dst], #4
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lsr data2, data2, #32
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1:
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tbz tmp1, #4, 1f
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strh data2_w, [dst], #2
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lsr data2, data2, #16
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1:
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tbz tmp1, #3, 1f
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strb data2_w, [dst]
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1:
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ret
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.Lmisaligned:
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tbz src, #0, 1f
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ldrb data1_w, [src], #1
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strb data1_w, [dst], #1
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cbnz data1_w, 1f
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ret
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1:
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tbz src, #1, 1f
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ldrb data1_w, [src], #1
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strb data1_w, [dst], #1
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cbz data1_w, .Ldone
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ldrb data2_w, [src], #1
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strb data2_w, [dst], #1
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cbnz data2_w, 1f
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.Ldone:
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ret
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1:
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tbz src, #2, 1f
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ldr data1_w, [src], #4
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// Check for a zero.
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sub has_nul1_w, data1_w, zeroones_w
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bic has_nul1_w, has_nul1_w, data1_w
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ands has_nul1_w, has_nul1_w, #0x80808080
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b.ne .Lnul_in_data1
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str data1_w, [dst], #4
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1:
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tbz src, #3, .Lloop
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ldr data1, [src], #8
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// Check for a zero.
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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bics has_nul1, tmp1, tmp2
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b.ne .Lnul_in_data1
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str data1, [dst], #8
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b .Lloop
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END(strcpy)
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#define STRCPY
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#include "string_copy.S"
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243
libc/arch-arm64/generic/bionic/string_copy.S
Normal file
243
libc/arch-arm64/generic/bionic/string_copy.S
Normal file
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@ -0,0 +1,243 @@
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/*
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* Copyright (C) 2014 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Copyright (c) 2014, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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||||
notice, this list of conditions and the following disclaimer.
|
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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*/
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#if !defined(STPCPY) && !defined(STRCPY)
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#error "Either STPCPY or STRCPY must be defined."
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#endif
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#include <private/bionic_asm.h>
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/* Arguments and results. */
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#if defined(STPCPY)
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#define dst x0
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#elif defined(STRCPY)
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#define dstin x0
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#endif
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#define src x1
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/* Locals and temporaries. */
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#if defined(STRCPY)
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#define dst x2
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#endif
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#define data1 x3
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#define data1_w w3
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#define data2 x4
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#define data2_w w4
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#define has_nul1 x5
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#define has_nul1_w w5
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#define has_nul2 x6
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#define tmp1 x7
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#define tmp2 x8
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#define tmp3 x9
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#define tmp4 x10
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#define zeroones x11
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#define zeroones_w w11
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#define pos x12
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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#if defined(STPCPY)
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ENTRY(stpcpy)
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#elif defined(STRCPY)
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ENTRY(strcpy)
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#endif
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mov zeroones, #REP8_01
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#if defined(STRCPY)
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mov dst, dstin
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#endif
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ands tmp1, src, #15
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b.ne .Lmisaligned
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// NUL detection works on the principle that (X - 1) & (~X) & 0x80
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// (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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// can be done in parallel across the entire word.
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// The inner loop deals with two Dwords at a time. This has a
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// slightly higher start-up cost, but we should win quite quickly,
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// especially on cores with a high number of issue slots per
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// cycle, as we get much better parallelism out of the operations.
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.Lloop:
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ldp data1, data2, [src], #16
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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bic has_nul1, tmp1, tmp2
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cbnz has_nul1, .Lnul_in_data1
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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bic has_nul2, tmp3, tmp4
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cbnz has_nul2, .Lnul_in_data2
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// No NUL in either register, copy it in a single instruction.
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stp data1, data2, [dst], #16
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b .Lloop
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.Lnul_in_data1:
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rev has_nul1, has_nul1
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clz pos, has_nul1
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add tmp1, pos, #0x8
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tbz tmp1, #6, 1f
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#if defined(STPCPY)
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str data1, [dst], #7
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#elif defined(STRCPY)
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str data1, [dst]
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#endif
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ret
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1:
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tbz tmp1, #5, 1f
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str data1_w, [dst], #4
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lsr data1, data1, #32
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1:
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tbz tmp1, #4, 1f
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strh data1_w, [dst], #2
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lsr data1, data1, #16
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1:
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tbz tmp1, #3, 1f
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strb data1_w, [dst]
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#if defined(STPCPY)
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ret
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#endif
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1:
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#if defined(STPCPY)
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// Back up one so that dst points to the '\0' string terminator.
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sub dst, dst, #1
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#endif
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ret
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.Lnul_in_data2:
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str data1, [dst], #8
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rev has_nul2, has_nul2
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clz pos, has_nul2
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add tmp1, pos, #0x8
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tbz tmp1, #6, 1f
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#if defined(STPCPY)
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str data2, [dst], #7
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#elif defined(STRCPY)
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str data2, [dst]
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#endif
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ret
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1:
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tbz tmp1, #5, 1f
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str data2_w, [dst], #4
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lsr data2, data2, #32
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1:
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tbz tmp1, #4, 1f
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strh data2_w, [dst], #2
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lsr data2, data2, #16
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1:
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tbz tmp1, #3, 1f
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strb data2_w, [dst]
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#if defined(STPCPY)
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ret
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#endif
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1:
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#if defined(STPCPY)
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// Back up one so that dst points to the '\0' string terminator.
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sub dst, dst, #1
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#endif
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ret
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.Lmisaligned:
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tbz src, #0, 1f
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ldrb data1_w, [src], #1
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strb data1_w, [dst], #1
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cbnz data1_w, 1f
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#if defined(STPCPY)
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// Back up one so that dst points to the '\0' string terminator.
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sub dst, dst, #1
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#endif
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ret
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1:
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tbz src, #1, 1f
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ldrb data1_w, [src], #1
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strb data1_w, [dst], #1
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cbz data1_w, .Ldone
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ldrb data2_w, [src], #1
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strb data2_w, [dst], #1
|
||||
cbnz data2_w, 1f
|
||||
.Ldone:
|
||||
#if defined(STPCPY)
|
||||
// Back up one so that dst points to the '\0' string terminator.
|
||||
sub dst, dst, #1
|
||||
#endif
|
||||
ret
|
||||
1:
|
||||
tbz src, #2, 1f
|
||||
ldr data1_w, [src], #4
|
||||
// Check for a zero.
|
||||
sub has_nul1_w, data1_w, zeroones_w
|
||||
bic has_nul1_w, has_nul1_w, data1_w
|
||||
ands has_nul1_w, has_nul1_w, #0x80808080
|
||||
b.ne .Lnul_in_data1
|
||||
str data1_w, [dst], #4
|
||||
1:
|
||||
tbz src, #3, .Lloop
|
||||
ldr data1, [src], #8
|
||||
// Check for a zero.
|
||||
sub tmp1, data1, zeroones
|
||||
orr tmp2, data1, #REP8_7f
|
||||
bics has_nul1, tmp1, tmp2
|
||||
b.ne .Lnul_in_data1
|
||||
str data1, [dst], #8
|
||||
b .Lloop
|
||||
#if defined(STPCPY)
|
||||
END(stpcpy)
|
||||
#elif defined(STRCPY)
|
||||
END(strcpy)
|
||||
#endif
|
||||
|
|
@ -3,6 +3,7 @@ libc_bionic_src_files_arm64 += \
|
|||
arch-arm64/generic/bionic/memcpy.S \
|
||||
arch-arm64/generic/bionic/memmove.S \
|
||||
arch-arm64/generic/bionic/memset.S \
|
||||
arch-arm64/generic/bionic/stpcpy.S \
|
||||
arch-arm64/generic/bionic/strchr.S \
|
||||
arch-arm64/generic/bionic/strcmp.S \
|
||||
arch-arm64/generic/bionic/strcpy.S \
|
||||
|
|
|
|||
Loading…
Reference in a new issue