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Merge "riscv64: fix <fenv.h> tests."

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Treehugger Robot 2022-10-19 04:20:36 +00:00 committed by Gerrit Code Review
commit d33a5c63a8
1 changed files with 6 additions and 3 deletions
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9
tests/fenv_test.cpp
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@ -202,9 +202,10 @@ TEST(fenv, fedisableexcept_fegetexcept) {
TEST(fenv, feenableexcept_fegetexcept) { TEST(fenv, feenableexcept_fegetexcept) {
#if !defined(ANDROID_HOST_MUSL) #if !defined(ANDROID_HOST_MUSL)
#if defined(__aarch64__) || defined(__arm__) #if defined(__aarch64__) || defined(__arm__) || defined(__riscv)
// ARM doesn't support this. They used to if you go back far enough, but it was removed in // ARM and RISC-V don't support hardware trapping of floating point
// the Cortex-A8 between r3p1 and r3p2. // exceptions. ARM used to if you go back far enough, but it was
// removed in the Cortex-A8 between r3p1 and r3p2. RISC-V never has.
ASSERT_EQ(-1, feenableexcept(FE_INVALID)); ASSERT_EQ(-1, feenableexcept(FE_INVALID));
ASSERT_EQ(0, fegetexcept()); ASSERT_EQ(0, fegetexcept());
ASSERT_EQ(-1, feenableexcept(FE_DIVBYZERO)); ASSERT_EQ(-1, feenableexcept(FE_DIVBYZERO));
@ -215,8 +216,10 @@ TEST(fenv, feenableexcept_fegetexcept) {
ASSERT_EQ(0, fegetexcept()); ASSERT_EQ(0, fegetexcept());
ASSERT_EQ(-1, feenableexcept(FE_INEXACT)); ASSERT_EQ(-1, feenableexcept(FE_INEXACT));
ASSERT_EQ(0, fegetexcept()); ASSERT_EQ(0, fegetexcept());
#if defined(_FE_DENORMAL) // riscv64 doesn't support this.
ASSERT_EQ(-1, feenableexcept(FE_DENORMAL)); ASSERT_EQ(-1, feenableexcept(FE_DENORMAL));
ASSERT_EQ(0, fegetexcept()); ASSERT_EQ(0, fegetexcept());
#endif
#else #else
// We can't recover from SIGFPE, so sacrifice a child... // We can't recover from SIGFPE, so sacrifice a child...
pid_t pid = fork(); pid_t pid = fork();