Commit graph

24 commits

Author SHA1 Message Date
Nick Desaulniers
c574f79afa Clean up __always_inline
While studying the implementation of POSIX pthread_rwlock* functions, I noticed
that two functions were marked __always_inline twice. "They must really mean it
this time."

Also add back `inline` keyword to one other usage of __always_inline to be
consistent with other uses of __always_inline throughout the codebase.

Change-Id: Ibf9eaed5fc9fd03afcdd969cff82dec71a8ce30f
2024-04-17 10:50:41 -07:00
Elliott Hughes
9e892499d9 riscv64: use L() in the handful of places we didn't already.
Change-Id: If34ae7a0eb3f7d0bd84018de4b987fd437decf58
2024-04-08 16:32:25 +00:00
Elliott Hughes
d7831208b2 Fix assembler warnings.
clang complains if you define a symbol and _then_ make it weak, rather
than the other way round:

  /tmp/setjmp-c3c977.s:90:1: warning: sigsetjmp changed binding to STB_WEAK
  .weak sigsetjmp;
  ^

Test: treehugger
Change-Id: Iee6b0ea456bb2e92aea810ce45f171caabaa89d2
2024-01-23 22:06:19 +00:00
Kenny Gong
066f4b778b riscv64: correct comparison logic of have_fast_v
Change-Id: I47fdc0900a8edf878e99a57d6f06ff6e12ca74f2
Signed-off-by: Kenny Gong <kenny.gong@intel.com>
2023-11-23 11:14:45 +08:00
Elliott Hughes
aefe999d92 string/memory functions: avoid qemu bugs/performance issues.
Use V on real hardware, but GC on qemu.

Change-Id: I419546d94555540e14a14dcc52bd99413cbbcfa1
2023-11-15 15:49:57 -08:00
Prashanth Swaminathan
a4d7102cf2 Temporarily fall back to non-V memcmp
Investigation revealed that the vector instructions in the assembly
implementation of memcmp seem to be putting QEMU into a bad state. This
code sometimes results in a SIGILL.

Temporarily disable the vector instructions for just this function.

Bug: 306514350
Test: Verified boot on AOSP CF image.
Change-Id: I184762354092b4b500c78a29a10db18cef0dab90
2023-10-30 18:04:20 -07:00
Elliott Hughes
7d13666b53 riscv64: fix ODR violations.
Rather than do the work to fix the ODR violations while preserving non-V,
let's just remove the non-V code. Android will require V anyway, and
anyone trying to work on a non-V system in the meantime already needs
a bunch of patches to the build system and ART, so one more shouldn't
hurt too much.

Test: treehugger
Change-Id: Iab43d8a80d99a4d045b0008dbea4e7e8696d1167
2023-10-27 16:42:52 -07:00
Elliott Hughes
1b2e844745 Fix riscv64 stpcpy().
We were copying the data fine, but the return value was one vector
length too far (but also not taking into account the actual number of
bytes in the last transfer).

Also move the stpcpy() tests to EXPECT_EQ() so we get all the details
of the failure at once.

Test: treehugger
Change-Id: I76bf02c8a31f40722acb7c9fd8e301d50e405bf8
2023-10-26 17:50:16 -07:00
Elliott Hughes
3d84338eb7 riscv64: add vector stpcpy().
Bug: https://github.com/google/android-riscv64/issues/107
Test: treehugger
Change-Id: Ic1fb9da974769d2767ea2c092a2e97e095612e6e
2023-10-03 00:39:42 +00:00
Elliott Hughes
bc192cff55 Add the L() macro for local labels to <private/bionic_asm.h>.
This lets us remove the riscv64 "sys/asm.h" file. It turns out everyone
loves this macro --- tons of x86 and arm assembler is already using it!

I'll clean up some of the now-duplicate definitions separately, and I'll
move the assembler we wrote ourselves over to this macro (rather than
the current `.L_foo` style) too.

Test: built riscv64 _and_ arm/arm64 _and_ x86/x86-64
Change-Id: If3f93c9b71094a8bed1fd1bb81bb83ec60ce409e
2023-08-04 15:12:30 -07:00
Yun Hsiang
40a82d005c Implement rvv version mem* and str* for riscv64
Add vector version mem* and str* functions and only build them when the
vector extension is enabled.
The original implementation comes from
https://github.com/sifive/sifive-libc, which we agree to contribute to
the Android Open Source Project.

Test: mma

Change-Id: I11b671a5bc571d7c783a657f272f282df7d16c29
Signed-off-by: Yun Hsiang <yun.hsiang@sifive.com>
2023-05-31 09:32:42 +08:00
Elliott Hughes
7dd3896fe1 riscv64: switch from x18 to gp for shadow call stack.
We want to give back a useful callee-saved general purpose
register (x18) that was only "chosen" because it was what llvm
allowed for historical reasons. gp is a better choice because it's
effectively unused otherwise anyway.

Unfortunately, that means we need extra space in jmp_buf (which I've
reserved in an earlier change, e7b3b8b467),
so let's rearrange the entries in jmp_buf to match their order in the
register file.

Bug: https://github.com/google/android-riscv64/issues/72
Bug: http://b/277909695
Test: treehugger
Change-Id: Ia629409a894c1a83d2052885702bbdd895c758e1
2023-04-12 14:19:38 -07:00
Elliott Hughes
060cd2438c Merge "riscv64 SCS support." 2023-03-21 22:10:56 +00:00
caowencheng
9a39eb3469 Increase the implementation of __memcpy_chk assembly
Use __memcpy_chk assembly to replace the implementation of c functions, which can reduce the use of instructions

Test: llvm-objdump

Change-Id: I5d75601626dc997626f6173d53af301183a64004
Signed-off-by: caowencheng <caowencheng@eswincomputing.com>
2023-03-21 02:05:14 +00:00
Elliott Hughes
6cb7db2b03 Merge "riscv64: use tail for tail calls." 2023-03-08 21:13:37 +00:00
Elliott Hughes
b0d3f0bcef riscv64: use tail for tail calls.
Don't assume that a `j` will always be in range. Let the toolchain
come up with the shortest sequence that will actually work.

Test: llvm-objdump -d
Change-Id: I497a68ecae434aad173c2b1c8024aed3756b8440
2023-03-08 18:22:29 +00:00
caowencheng
d27c83fbd4 Fix the compile errors "R_RISCV_JAL out of rang" when the jump range is greater than 1M memory space between vfork and __set_errno_internal
the "tail" command is used here, let the compiler decide
which instruction to use. when the call distance is less
than 1M, it will be compiled into "jr" command, and when
the distance is greater than 1M, it will be compiled
into "aupic" and "jr" command.

Test: make libc
Change-Id: I80d099d25c7cc2439a297d8afc65abeb5a7a360c
Signed-off-by: caowencheng <caowencheng@eswincomputing.com>
2023-03-08 01:44:50 +00:00
caowencheng
ab457f9022 memset_chk into assembly file
Writing an assembly file can reduce several
assembly instructions, and compare it through
the disassembly of this file

Test: make libc
Change-Id: Ifdcc9c76742cc95b2ad9e3c14fac4796c36e12e6
Signed-off-by: caowencheng <caowencheng@eswincomputing.com>
2023-03-06 07:23:10 +00:00
Elliott Hughes
9a7155dbbd riscv64 SCS support.
Bug: https://github.com/google/android-riscv64/issues/55
Test: treehugger
Change-Id: I05d48a07a302305126942d38529ffa280640c7b7
2023-02-23 01:21:07 +00:00
Elliott Hughes
6a1dc51679 riscv64: don't go via the PLT for setjmp.
I don't think we need or want to do this. Most other architectures
don't.

Test: bionic-unit-tests-static
Change-Id: I3ad31926909caf0a37e73ac6cbac1fecd02ea6de
2022-10-26 19:53:35 +00:00
Elliott Hughes
45a84869c4 riscv64: fix setjmp so we're actually using the right cookie!
Test: setjmp.setjmp_smoke
Change-Id: Ia0a160656b9e83cdec611ac196b1ae62f082ab6c
2022-10-18 23:04:12 +00:00
Elliott Hughes
c800a3bd02 riscv64: don't store both arguments in the same place on the stack.
All the pthread tests are, unsurprisingly, broken without this fix.

Test: treehugger
Change-Id: Ia4c6ac077f3bbd749201ae8d200ec99093f7f4bc
2022-10-18 20:01:58 +00:00
Elliott Hughes
e1905ed629 riscv64 setjmp.
Signed-off-by: Mao Han <han_mao@linux.alibaba.com>
Signed-off-by: Xia Lifang <lifang_xia@linux.alibaba.com>
Signed-off-by: Chen Guoyin <chenguoyin.cgy@linux.alibaba.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
Signed-off-by: Lu Xufan <luxufan@iscas.ac.cn>
Test: m
Change-Id: I02cf117f67bda74516e4de8cd6f4c05efdb9a85b
2022-10-17 23:23:36 +00:00
Elliott Hughes
ebc19a9ccb riscv64: add bionic assembler and string functions.
Pull the portable C string functions from FreeBSD, and do fairly literal
translations of our existing .S files for the bionic-specific stuff.

Test: treehugger
Change-Id: Id42e5b8a51ed73155be020d74edd7011a2103574
2022-10-14 23:25:36 +00:00