6c8a2f2a5b
We simply copy the stuff we need from cutils headers. A future patch will change cutils to include the private <bionic_atomic_inline.h> Change-Id: Ib6fd9a03bc9e337ce867bd606dc94c2b4438480a
107 lines
3.3 KiB
C
107 lines
3.3 KiB
C
/*
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* Copyright (C) 2010 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BIONIC_ATOMIC_INLINE_H
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#define BIONIC_ATOMIC_INLINE_H
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/*
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* Inline declarations and macros for some special-purpose atomic
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* operations. These are intended for rare circumstances where a
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* memory barrier needs to be issued inline rather than as a function
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* call.
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*
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* Most code should not use these.
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*
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* Anything that does include this file must set ANDROID_SMP to either
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* 0 or 1, indicating compilation for UP or SMP, respectively.
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*
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* Macros defined in this header:
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*
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* void ANDROID_MEMBAR_FULL(void)
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* Full memory barrier. Provides a compiler reordering barrier, and
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* on SMP systems emits an appropriate instruction.
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*/
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#if !defined(ANDROID_SMP)
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# error "Must define ANDROID_SMP before including atomic-inline.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Define the full memory barrier for an SMP system. This is
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* platform-specific.
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*/
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#ifdef __arm__
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#include <machine/cpu-features.h>
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/*
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* For ARMv6K we need to issue a specific MCR instead of the DMB, since
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* that wasn't added until v7. For anything older, SMP isn't relevant.
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* Since we don't have an ARMv6K to test with, we're not going to deal
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* with that now.
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*
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* The DMB instruction is found in the ARM and Thumb2 instruction sets.
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* This will fail on plain 16-bit Thumb.
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*/
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#if defined(__ARM_HAVE_DMB)
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# define _ANDROID_MEMBAR_FULL_SMP() \
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do { __asm__ __volatile__ ("dmb" ::: "memory"); } while (0)
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#else
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# define _ANDROID_MEMBAR_FULL_SMP() ARM_SMP_defined_but_no_DMB()
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#endif
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#elif defined(__i386__) || defined(__x86_64__)
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/*
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* For recent x86, we can use the SSE2 mfence instruction.
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*/
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# define _ANDROID_MEMBAR_FULL_SMP() \
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do { __asm__ __volatile__ ("mfence" ::: "memory"); } while (0)
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#else
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/*
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* Implementation not defined for this platform. Hopefully we're building
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* in uniprocessor mode.
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*/
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# define _ANDROID_MEMBAR_FULL_SMP() SMP_barrier_not_defined_for_platform()
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#endif
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/*
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* Full barrier. On uniprocessors this is just a compiler reorder barrier,
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* which ensures that the statements appearing above the barrier in the C/C++
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* code will be issued after the statements appearing below the barrier.
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*
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* For SMP this also includes a memory barrier instruction. On an ARM
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* CPU this means that the current core will flush pending writes, wait
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* for pending reads to complete, and discard any cached reads that could
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* be stale. Other CPUs may do less, but the end result is equivalent.
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*/
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#if ANDROID_SMP != 0
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# define ANDROID_MEMBAR_FULL() _ANDROID_MEMBAR_FULL_SMP()
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#else
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# define ANDROID_MEMBAR_FULL() \
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do { __asm__ __volatile__ ("" ::: "memory"); } while (0)
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#endif
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // BIONIC_ATOMIC_INLINE_H
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