b640e031a8
This change resolves Fortify1_{gcc|clang}_DeathTest.* test failures.
Change-Id: Ia936c159323bdf8e9577160ee92b99e66e6793ea
448 lines
14 KiB
ArmAsm
448 lines
14 KiB
ArmAsm
/*
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* Copyright (c) 2013
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* MIPS Technologies, Inc., California.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef __ANDROID__
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# include <private/bionic_asm.h>
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# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
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#elif _LIBC
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# include <sysdep.h>
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# include <regdef.h>
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# include <sys/asm.h>
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# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
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#elif _COMPILING_NEWLIB
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# include "machine/asm.h"
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# include "machine/regdef.h"
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# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE
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#else
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# include <regdef.h>
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# include <sys/asm.h>
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#endif
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/* Check to see if the MIPS architecture we are compiling for supports
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prefetching. */
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#if (__mips == 4) || (__mips == 5) || (__mips == 32) || (__mips == 64)
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# ifndef DISABLE_PREFETCH
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# define USE_PREFETCH
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# endif
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#endif
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#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32))
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# ifndef DISABLE_DOUBLE
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# define USE_DOUBLE
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# endif
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#endif
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#ifndef USE_DOUBLE
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# ifndef DISABLE_DOUBLE_ALIGN
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# define DOUBLE_ALIGN
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# endif
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#endif
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/* Some asm.h files do not have the L macro definition. */
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#ifndef L
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# if _MIPS_SIM == _ABIO32
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# define L(label) $L ## label
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# else
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# define L(label) .L ## label
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# endif
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#endif
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/* Some asm.h files do not have the PTR_ADDIU macro definition. */
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#ifndef PTR_ADDIU
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# if _MIPS_SIM == _ABIO32
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# define PTR_ADDIU addiu
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# else
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# define PTR_ADDIU daddiu
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# endif
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#endif
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/* New R6 instructions that may not be in asm.h. */
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#ifndef PTR_LSA
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# if _MIPS_SIM == _ABIO32
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# define PTR_LSA lsa
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# else
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# define PTR_LSA dlsa
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# endif
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#endif
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/* Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE
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or PREFETCH_STORE_STREAMED offers a large performance advantage
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but PREPAREFORSTORE has some special restrictions to consider.
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Prefetch with the 'prepare for store' hint does not copy a memory
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location into the cache, it just allocates a cache line and zeros
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it out. This means that if you do not write to the entire cache
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line before writing it out to memory some data will get zero'ed out
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when the cache line is written back to memory and data will be lost.
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There are ifdef'ed sections of this memcpy to make sure that it does not
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do prefetches on cache lines that are not going to be completely written.
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This code is only needed and only used when PREFETCH_STORE_HINT is set to
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PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are
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less than MAX_PREFETCH_SIZE bytes and if the cache line is larger it will
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not work correctly. */
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#ifdef USE_PREFETCH
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# define PREFETCH_HINT_STORE 1
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# define PREFETCH_HINT_STORE_STREAMED 5
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# define PREFETCH_HINT_STORE_RETAINED 7
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# define PREFETCH_HINT_PREPAREFORSTORE 30
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/* If we have not picked out what hints to use at this point use the
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standard load and store prefetch hints. */
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# ifndef PREFETCH_STORE_HINT
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# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE
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# endif
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/* We double everything when USE_DOUBLE is true so we do 2 prefetches to
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get 64 bytes in that case. The assumption is that each individual
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prefetch brings in 32 bytes. */
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# ifdef USE_DOUBLE
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# define PREFETCH_CHUNK 64
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# define PREFETCH_FOR_STORE(chunk, reg) \
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pref PREFETCH_STORE_HINT, (chunk)*64(reg); \
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pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg)
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# else
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# define PREFETCH_CHUNK 32
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# define PREFETCH_FOR_STORE(chunk, reg) \
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pref PREFETCH_STORE_HINT, (chunk)*32(reg)
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# endif
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/* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less
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than PREFETCH_CHUNK, the assumed size of each prefetch. If the real size
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of a prefetch is greater than MAX_PREFETCH_SIZE and the PREPAREFORSTORE
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hint is used, the code will not work correctly. If PREPAREFORSTORE is not
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used than MAX_PREFETCH_SIZE does not matter. */
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# define MAX_PREFETCH_SIZE 128
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/* PREFETCH_LIMIT is set based on the fact that we never use an offset greater
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than 5 on a STORE prefetch and that a single prefetch can never be larger
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than MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because
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we actually do two prefetches in that case, one 32 bytes after the other. */
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# ifdef USE_DOUBLE
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# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE
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# else
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# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE
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# endif
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# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \
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&& ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE)
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/* We cannot handle this because the initial prefetches may fetch bytes that
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are before the buffer being copied. We start copies with an offset
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of 4 so avoid this situation when using PREPAREFORSTORE. */
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# error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small."
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# endif
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#else /* USE_PREFETCH not defined */
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# define PREFETCH_FOR_STORE(offset, reg)
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#endif
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#if __mips_isa_rev > 5
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# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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# undef PREFETCH_STORE_HINT
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# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED
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# endif
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# define R6_CODE
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#endif
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/* We load/store 64 bits at a time when USE_DOUBLE is true.
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The C_ prefix stands for CHUNK and is used to avoid macro name
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conflicts with system header files. */
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#ifdef USE_DOUBLE
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# define C_ST sd
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# if __MIPSEB
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# define C_STHI sdl /* high part is left in big-endian */
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# else
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# define C_STHI sdr /* high part is right in little-endian */
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# endif
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#else
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# define C_ST sw
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# if __MIPSEB
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# define C_STHI swl /* high part is left in big-endian */
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# else
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# define C_STHI swr /* high part is right in little-endian */
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# endif
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#endif
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/* Bookkeeping values for 32 vs. 64 bit mode. */
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#ifdef USE_DOUBLE
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# define NSIZE 8
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# define NSIZEMASK 0x3f
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# define NSIZEDMASK 0x7f
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#else
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# define NSIZE 4
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# define NSIZEMASK 0x1f
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# define NSIZEDMASK 0x3f
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#endif
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#define UNIT(unit) ((unit)*NSIZE)
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#define UNITM1(unit) (((unit)*NSIZE)-1)
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#ifdef __ANDROID__
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LEAF(__memset_chk,0)
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#else
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LEAF(__memset_chk)
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#endif
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.set noreorder
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sltu t2, a3, a2
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beq t2, zero, memset
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nop
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.cpsetup t9, t8, __memset_chk
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LA t9, __memset_chk_fail
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jr t9
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nop
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.set reorder
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END(__memset_chk)
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#ifdef __ANDROID__
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LEAF(memset,0)
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#else
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LEAF(memset)
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#endif
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.set nomips16
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.set noreorder
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/* If the size is less than 2*NSIZE (8 or 16), go to L(lastb). Regardless of
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size, copy dst pointer to v0 for the return value. */
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slti t2,a2,(2 * NSIZE)
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bne t2,zero,L(lastb)
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move v0,a0
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/* If memset value is not zero, we copy it to all the bytes in a 32 or 64
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bit word. */
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beq a1,zero,L(set0) /* If memset value is zero no smear */
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PTR_SUBU a3,zero,a0
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nop
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/* smear byte into 32 or 64 bit word */
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#if ((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2)
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# ifdef USE_DOUBLE
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dins a1, a1, 8, 8 /* Replicate fill byte into half-word. */
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dins a1, a1, 16, 16 /* Replicate fill byte into word. */
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dins a1, a1, 32, 32 /* Replicate fill byte into dbl word. */
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# else
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ins a1, a1, 8, 8 /* Replicate fill byte into half-word. */
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ins a1, a1, 16, 16 /* Replicate fill byte into word. */
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# endif
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#else
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# ifdef USE_DOUBLE
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and a1,0xff
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dsll t2,a1,8
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or a1,t2
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dsll t2,a1,16
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or a1,t2
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dsll t2,a1,32
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or a1,t2
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# else
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and a1,0xff
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sll t2,a1,8
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or a1,t2
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sll t2,a1,16
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or a1,t2
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# endif
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#endif
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/* If the destination address is not aligned do a partial store to get it
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aligned. If it is already aligned just jump to L(aligned). */
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L(set0):
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#ifndef R6_CODE
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andi t2,a3,(NSIZE-1) /* word-unaligned address? */
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beq t2,zero,L(aligned) /* t2 is the unalignment count */
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PTR_SUBU a2,a2,t2
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C_STHI a1,0(a0)
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PTR_ADDU a0,a0,t2
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#else /* R6_CODE */
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andi t2,a0,(NSIZE-1)
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lapc t9,L(atable)
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PTR_LSA t9,t2,t9,2
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jrc t9
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L(atable):
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bc L(aligned)
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# ifdef USE_DOUBLE
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bc L(lb7)
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bc L(lb6)
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bc L(lb5)
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bc L(lb4)
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# endif
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bc L(lb3)
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bc L(lb2)
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bc L(lb1)
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L(lb7):
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sb a1,6(a0)
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L(lb6):
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sb a1,5(a0)
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L(lb5):
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sb a1,4(a0)
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L(lb4):
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sb a1,3(a0)
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L(lb3):
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sb a1,2(a0)
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L(lb2):
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sb a1,1(a0)
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L(lb1):
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sb a1,0(a0)
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li t9,NSIZE
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subu t2,t9,t2
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PTR_SUBU a2,a2,t2
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PTR_ADDU a0,a0,t2
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#endif /* R6_CODE */
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L(aligned):
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/* If USE_DOUBLE is not set we may still want to align the data on a 16
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byte boundry instead of an 8 byte boundry to maximize the opportunity
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of proAptiv chips to do memory bonding (combining two sequential 4
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byte stores into one 8 byte store). We know there are at least 4 bytes
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left to store or we would have jumped to L(lastb) earlier in the code. */
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#ifdef DOUBLE_ALIGN
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andi t2,a3,4
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beq t2,zero,L(double_aligned)
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PTR_SUBU a2,a2,t2
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sw a1,0(a0)
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PTR_ADDU a0,a0,t2
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L(double_aligned):
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#endif
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/* Now the destination is aligned to (word or double word) aligned address
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Set a2 to count how many bytes we have to copy after all the 64/128 byte
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chunks are copied and a3 to the dest pointer after all the 64/128 byte
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chunks have been copied. We will loop, incrementing a0 until it equals
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a3. */
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andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */
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beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */
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PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */
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PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */
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/* When in the loop we may prefetch with the 'prepare to store' hint,
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in this case the a0+x should not be past the "t0-32" address. This
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means: for x=128 the last "safe" a0 address is "t0-160". Alternatively,
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for x=64 the last "safe" a0 address is "t0-96" In the current version we
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will use "prefetch hint,128(a0)", so "t0-160" is the limit. */
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#if defined(USE_PREFETCH) \
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&& (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */
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PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */
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#endif
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#if defined(USE_PREFETCH) \
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&& (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE)
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PREFETCH_FOR_STORE (1, a0)
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PREFETCH_FOR_STORE (2, a0)
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PREFETCH_FOR_STORE (3, a0)
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#endif
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L(loop16w):
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#if defined(USE_PREFETCH) \
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&& (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE)
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sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */
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bgtz v1,L(skip_pref)
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nop
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#endif
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#ifndef R6_CODE
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PREFETCH_FOR_STORE (4, a0)
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PREFETCH_FOR_STORE (5, a0)
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#else
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PREFETCH_FOR_STORE (2, a0)
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#endif
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L(skip_pref):
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C_ST a1,UNIT(0)(a0)
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C_ST a1,UNIT(1)(a0)
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C_ST a1,UNIT(2)(a0)
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C_ST a1,UNIT(3)(a0)
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C_ST a1,UNIT(4)(a0)
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C_ST a1,UNIT(5)(a0)
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C_ST a1,UNIT(6)(a0)
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C_ST a1,UNIT(7)(a0)
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C_ST a1,UNIT(8)(a0)
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C_ST a1,UNIT(9)(a0)
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C_ST a1,UNIT(10)(a0)
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C_ST a1,UNIT(11)(a0)
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C_ST a1,UNIT(12)(a0)
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C_ST a1,UNIT(13)(a0)
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C_ST a1,UNIT(14)(a0)
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C_ST a1,UNIT(15)(a0)
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PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */
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bne a0,a3,L(loop16w)
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nop
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move a2,t8
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/* Here we have dest word-aligned but less than 64-bytes or 128 bytes to go.
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Check for a 32(64) byte chunk and copy if if there is one. Otherwise
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jump down to L(chk1w) to handle the tail end of the copy. */
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L(chkw):
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andi t8,a2,NSIZEMASK /* is there a 32-byte/64-byte chunk. */
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/* the t8 is the reminder count past 32-bytes */
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beq a2,t8,L(chk1w)/* when a2==t8, no 32-byte chunk */
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nop
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C_ST a1,UNIT(0)(a0)
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C_ST a1,UNIT(1)(a0)
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C_ST a1,UNIT(2)(a0)
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C_ST a1,UNIT(3)(a0)
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C_ST a1,UNIT(4)(a0)
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C_ST a1,UNIT(5)(a0)
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C_ST a1,UNIT(6)(a0)
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C_ST a1,UNIT(7)(a0)
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PTR_ADDIU a0,a0,UNIT(8)
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/* Here we have less than 32(64) bytes to set. Set up for a loop to
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copy one word (or double word) at a time. Set a2 to count how many
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bytes we have to copy after all the word (or double word) chunks are
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copied and a3 to the dest pointer after all the (d)word chunks have
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been copied. We will loop, incrementing a0 until a0 equals a3. */
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L(chk1w):
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andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */
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beq a2,t8,L(lastb)
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PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */
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PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */
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/* copying in words (4-byte or 8 byte chunks) */
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L(wordCopy_loop):
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PTR_ADDIU a0,a0,UNIT(1)
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bne a0,a3,L(wordCopy_loop)
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C_ST a1,UNIT(-1)(a0)
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/* Copy the last 8 (or 16) bytes */
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L(lastb):
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blez a2,L(leave)
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PTR_ADDU a3,a0,a2 /* a3 is the last dst address */
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L(lastbloop):
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PTR_ADDIU a0,a0,1
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bne a0,a3,L(lastbloop)
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sb a1,-1(a0)
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L(leave):
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j ra
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nop
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.set at
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.set reorder
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END(memset)
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#ifndef __ANDROID__
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# ifdef _LIBC
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libc_hidden_builtin_def (memset)
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libc_hidden_builtin_def (__memset_chk)
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# endif
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#endif
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