221 lines
6.1 KiB
ArmAsm
221 lines
6.1 KiB
ArmAsm
/*
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* Copyright (C) 2013 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <private/bionic_asm.h>
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// According to AARCH64 PCS document we need to save the following
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// registers:
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//
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// Core x19 - x30, sp (see section 5.1.1)
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// VFP d8 - d15 (see section 5.1.2)
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//
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// NOTE: All the registers saved here will have 64 bit vales.
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// AAPCS mandates that the higher part of q registers do not need to
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// be saved by the callee.
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#define _JB_SIGFLAG 0
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#define _JB_SIGMASK (_JB_SIGFLAG + 1)
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#define _JB_X30_SP (_JB_SIGMASK + 1)
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#define _JB_X28_X29 (_JB_X30_SP + 2)
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#define _JB_X26_X27 (_JB_X28_X29 + 2)
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#define _JB_X24_X25 (_JB_X26_X27 + 2)
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#define _JB_X22_X23 (_JB_X24_X25 + 2)
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#define _JB_X20_X21 (_JB_X22_X23 + 2)
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#define _JB_X19 (_JB_X20_X21 + 2)
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#define _JB_D14_D15 (_JB_X19 + 1)
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#define _JB_D12_D13 (_JB_D14_D15 + 2)
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#define _JB_D10_D11 (_JB_D12_D13 + 2)
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#define _JB_D8_D9 (_JB_D10_D11 + 2)
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#define MANGLE_REGISTERS 1
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.macro m_mangle_registers reg, sp_reg
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#if MANGLE_REGISTERS
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eor x19, x19, \reg
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eor x20, x20, \reg
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eor x21, x21, \reg
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eor x22, x22, \reg
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eor x23, x23, \reg
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eor x24, x24, \reg
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eor x25, x25, \reg
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eor x26, x26, \reg
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eor x27, x27, \reg
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eor x28, x28, \reg
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eor x29, x29, \reg
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eor x30, x30, \reg
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eor \sp_reg, \sp_reg, \reg
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#endif
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.endm
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.macro m_unmangle_registers reg, sp_reg
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m_mangle_registers \reg, sp_reg=\sp_reg
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.endm
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ENTRY(setjmp)
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mov w1, #1
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b sigsetjmp
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END(setjmp)
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ENTRY(_setjmp)
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mov w1, #0
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b sigsetjmp
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END(_setjmp)
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// int sigsetjmp(sigjmp_buf env, int save_signal_mask);
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ENTRY(sigsetjmp)
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stp x0, x30, [sp, #-16]!
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.cfi_def_cfa_offset 16
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.cfi_rel_offset x0, 0
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.cfi_rel_offset x30, 8
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// Get the cookie and store it along with the signal flag.
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mov x0, x1
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bl __bionic_setjmp_cookie_get
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mov x1, x0
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ldr x0, [sp, #0]
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str x1, [x0, #(_JB_SIGFLAG * 8)]
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// Do we need to save the signal mask?
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tbz w1, #0, 1f
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// Save the cookie for later.
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stp x1, xzr, [sp, #-16]!
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.cfi_adjust_cfa_offset 16
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// Save current signal mask.
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// The 'how' argument is ignored if new_mask is NULL.
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mov x1, #0 // NULL.
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add x2, x0, #(_JB_SIGMASK * 8) // old_mask.
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bl sigprocmask
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ldp x1, xzr, [sp], #16
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.cfi_adjust_cfa_offset -16
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1:
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// Restore original x0 and lr.
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ldp x0, x30, [sp], #16
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.cfi_adjust_cfa_offset -16
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.cfi_restore x0
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.cfi_restore x30
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// Mask off the signal flag bit.
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bic x1, x1, #1
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// Save core registers.
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mov x10, sp
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m_mangle_registers x1, sp_reg=x10
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stp x30, x10, [x0, #(_JB_X30_SP * 8)]
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stp x28, x29, [x0, #(_JB_X28_X29 * 8)]
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stp x26, x27, [x0, #(_JB_X26_X27 * 8)]
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stp x24, x25, [x0, #(_JB_X24_X25 * 8)]
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stp x22, x23, [x0, #(_JB_X22_X23 * 8)]
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stp x20, x21, [x0, #(_JB_X20_X21 * 8)]
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str x19, [x0, #(_JB_X19 * 8)]
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m_unmangle_registers x1, sp_reg=x10
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// Save floating point registers.
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stp d14, d15, [x0, #(_JB_D14_D15 * 8)]
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stp d12, d13, [x0, #(_JB_D12_D13 * 8)]
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stp d10, d11, [x0, #(_JB_D10_D11 * 8)]
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stp d8, d9, [x0, #(_JB_D8_D9 * 8)]
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mov w0, #0
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ret
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END(sigsetjmp)
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// void siglongjmp(sigjmp_buf env, int value);
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ENTRY(siglongjmp)
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// Do we need to restore the signal mask?
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ldr x2, [x0, #(_JB_SIGFLAG * 8)]
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tbz w2, #0, 1f
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stp x0, x30, [sp, #-16]!
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.cfi_adjust_cfa_offset 16
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.cfi_rel_offset x0, 0
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.cfi_rel_offset x30, 8
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// Restore signal mask.
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mov x19, x1 // Save 'value'.
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mov x2, x0
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mov x0, #2 // SIG_SETMASK
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add x1, x2, #(_JB_SIGMASK * 8) // new_mask.
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mov x2, #0 // NULL.
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bl sigprocmask
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mov x1, x19 // Restore 'value'.
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// Restore original x0 and lr.
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ldp x0, x30, [sp], #16
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.cfi_adjust_cfa_offset -16
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.cfi_restore x0
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.cfi_restore x30
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ldr x2, [x0, #(_JB_SIGFLAG * 8)]
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1:
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// Restore core registers.
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bic x2, x2, #1
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ldp x30, x10, [x0, #(_JB_X30_SP * 8)]
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ldp x28, x29, [x0, #(_JB_X28_X29 * 8)]
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ldp x26, x27, [x0, #(_JB_X26_X27 * 8)]
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ldp x24, x25, [x0, #(_JB_X24_X25 * 8)]
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ldp x22, x23, [x0, #(_JB_X22_X23 * 8)]
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ldp x20, x21, [x0, #(_JB_X20_X21 * 8)]
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ldr x19, [x0, #(_JB_X19 * 8)]
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m_unmangle_registers x2, sp_reg=x10
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mov sp, x10
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stp x0, x1, [sp, #-16]!
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.cfi_adjust_cfa_offset 16
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.cfi_rel_offset x0, 0
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.cfi_rel_offset x1, 8
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stp x30, xzr, [sp, #-16]!
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.cfi_adjust_cfa_offset 16
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.cfi_rel_offset x30, 0
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ldr x0, [x0, #(_JB_SIGFLAG * 8)]
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bl __bionic_setjmp_cookie_check
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ldp x30, xzr, [sp], #16
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.cfi_adjust_cfa_offset -16
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.cfi_restore x30
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ldp x0, x1, [sp], #16
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.cfi_adjust_cfa_offset -16
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.cfi_restore x0
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.cfi_restore x1
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// Restore floating point registers.
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ldp d14, d15, [x0, #(_JB_D14_D15 * 8)]
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ldp d12, d13, [x0, #(_JB_D12_D13 * 8)]
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ldp d10, d11, [x0, #(_JB_D10_D11 * 8)]
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ldp d8, d9, [x0, #(_JB_D8_D9 * 8)]
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// Set return value.
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cmp w1, wzr
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csinc w0, w1, wzr, ne
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ret
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END(siglongjmp)
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ALIAS_SYMBOL(longjmp, siglongjmp)
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ALIAS_SYMBOL(_longjmp, siglongjmp)
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