80ae69d11e
Kernel headers coming from: Git: https://android.googlesource.com/kernel/common/ Branch: android-mainline Tag: android-mainline-5.19 Test: Builds on coral. Test: All bionic unit tests pass on a coral device. Test: Able to log in to wembley system. Change-Id: I6fa6f6edb59f2cef990a7ba96877d9f2d3974c62
143 lines
5.4 KiB
C
143 lines
5.4 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _UAPI__ASM_PTRACE_H
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#define _UAPI__ASM_PTRACE_H
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#include <linux/types.h>
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#include <asm/hwcap.h>
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#include <asm/sve_context.h>
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#define PSR_MODE_EL0t 0x00000000
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#define PSR_MODE_EL1t 0x00000004
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#define PSR_MODE_EL1h 0x00000005
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#define PSR_MODE_EL2t 0x00000008
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#define PSR_MODE_EL2h 0x00000009
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#define PSR_MODE_EL3t 0x0000000c
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#define PSR_MODE_EL3h 0x0000000d
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#define PSR_MODE_MASK 0x0000000f
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#define PSR_MODE32_BIT 0x00000010
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#define PSR_F_BIT 0x00000040
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#define PSR_I_BIT 0x00000080
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#define PSR_A_BIT 0x00000100
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#define PSR_D_BIT 0x00000200
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#define PSR_BTYPE_MASK 0x00000c00
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#define PSR_SSBS_BIT 0x00001000
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#define PSR_PAN_BIT 0x00400000
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#define PSR_UAO_BIT 0x00800000
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#define PSR_DIT_BIT 0x01000000
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#define PSR_TCO_BIT 0x02000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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#define PSR_N_BIT 0x80000000
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#define PSR_BTYPE_SHIFT 10
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#define PSR_f 0xff000000
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#define PSR_s 0x00ff0000
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#define PSR_x 0x0000ff00
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#define PSR_c 0x000000ff
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#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
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#define PTRACE_SYSEMU 31
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#define PTRACE_SYSEMU_SINGLESTEP 32
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#define PTRACE_PEEKMTETAGS 33
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#define PTRACE_POKEMTETAGS 34
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#ifndef __ASSEMBLY__
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struct user_pt_regs {
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__u64 regs[31];
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__u64 sp;
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__u64 pc;
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__u64 pstate;
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};
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struct user_fpsimd_state {
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__uint128_t vregs[32];
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__u32 fpsr;
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__u32 fpcr;
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__u32 __reserved[2];
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};
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struct user_hwdebug_state {
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__u32 dbg_info;
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__u32 pad;
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struct {
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__u64 addr;
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__u32 ctrl;
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__u32 pad;
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} dbg_regs[16];
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};
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struct user_sve_header {
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__u32 size;
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__u32 max_size;
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__u16 vl;
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__u16 max_vl;
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__u16 flags;
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__u16 __reserved;
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};
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#define SVE_PT_REGS_MASK (1 << 0)
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#define SVE_PT_REGS_FPSIMD 0
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#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
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#define SVE_PT_VL_INHERIT ((1 << 17) >> 16)
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#define SVE_PT_VL_ONEXEC ((1 << 18) >> 16)
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#define SVE_PT_REGS_OFFSET ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
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#define SVE_PT_FPSIMD_SIZE(vq,flags) (sizeof(struct user_fpsimd_state))
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#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
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#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
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#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
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#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
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#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
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#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
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#define SVE_PT_SVE_ZREGS_OFFSET (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
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#define SVE_PT_SVE_ZREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
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#define SVE_PT_SVE_ZREGS_SIZE(vq) (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
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#define SVE_PT_SVE_PREGS_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
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#define SVE_PT_SVE_PREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
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#define SVE_PT_SVE_PREGS_SIZE(vq) (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - SVE_PT_SVE_PREGS_OFFSET(vq))
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#define SVE_PT_SVE_FFR_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
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#define SVE_PT_SVE_FPSR_OFFSET(vq) ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define SVE_PT_SVE_FPCR_OFFSET(vq) (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
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#define SVE_PT_SVE_SIZE(vq,flags) ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE - SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define SVE_PT_SIZE(vq,flags) (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) : ((((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD ? SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags) : SVE_PT_REGS_OFFSET)))
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struct user_pac_mask {
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__u64 data_mask;
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__u64 insn_mask;
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};
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struct user_pac_address_keys {
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__uint128_t apiakey;
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__uint128_t apibkey;
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__uint128_t apdakey;
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__uint128_t apdbkey;
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};
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struct user_pac_generic_keys {
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__uint128_t apgakey;
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};
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struct user_za_header {
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__u32 size;
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__u32 max_size;
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__u16 vl;
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__u16 max_vl;
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__u16 flags;
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__u16 __reserved;
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};
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#define ZA_PT_VL_INHERIT ((1 << 17) >> 16)
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#define ZA_PT_VL_ONEXEC ((1 << 18) >> 16)
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#define ZA_PT_ZA_OFFSET ((sizeof(struct user_za_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define ZA_PT_ZAV_OFFSET(vq,n) (ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
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#define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
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#define ZA_PT_SIZE(vq) (ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
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#endif
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#endif
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