405b8029a6
Change-Id: I2864dea04b3faf2d919165dcaa600af5b16c41c8 Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Raghu Gandham <raghu@mips.com>
211 lines
7.2 KiB
ArmAsm
211 lines
7.2 KiB
ArmAsm
/* $OpenBSD: setjmp.S,v 1.5 2005/08/07 16:40:15 espie Exp $ */
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/*
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* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Opsycon AB nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <machine/asm.h>
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#include <machine/regnum.h>
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#include <machine/signal.h>
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/*
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* setjmp, longjmp implementation for libc. this code depends
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* on the layout of the struct sigcontext in machine/signal.h.
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*
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*/
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FRAMESZ= MKFSIZ(2,6)
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A1OFF= FRAMESZ-4*REGSZ
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A0OFF= FRAMESZ-3*REGSZ
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GPOFF= FRAMESZ-2*REGSZ
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RAOFF= FRAMESZ-1*REGSZ
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#define FPREG64_S(FPR, OFF, BASE) \
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swc1 FPR, OFF(BASE) ; \
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mfhc1 t0, FPR ; \
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sw t0, OFF+4(BASE) ;
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#define FPREG64_L(FPR, OFF, BASE) \
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lw t0, OFF+4(BASE) ; \
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lw t1, OFF(BASE) ; \
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mtc1 t1, FPR ; \
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mthc1 t0, FPR ; \
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NON_LEAF(setjmp, FRAMESZ, ra)
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.mask 0x80000000, RAOFF
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PTR_SUBU sp, FRAMESZ # allocate stack frame
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SETUP_GP64(GPOFF, setjmp)
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SAVE_GP(GPOFF)
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.set reorder
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REG_S ra, RAOFF(sp) # save state
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REG_S a0, A0OFF(sp)
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move a0, zero # get current signal mask
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jal sigblock
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REG_L v1, A0OFF(sp) # v1 = jmpbuf
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REG_S v0, SC_MASK(v1) # save sc_mask = sigblock(0)
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REG_L a0, A0OFF(sp) # restore jmpbuf
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REG_L ra, RAOFF(sp)
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REG_S ra, SC_PC(a0) # sc_pc = return address
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#if defined(__mips64)
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dli v0, 0xACEDBADE # sigcontext magic number
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#else
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li v0, 0xACEDBADE # sigcontext magic number
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#endif
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REG_S v0, SC_REGS+ZERO*REGSZ(a0)
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REG_S s0, SC_REGS+S0*REGSZ(a0)
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REG_S s1, SC_REGS+S1*REGSZ(a0)
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REG_S s2, SC_REGS+S2*REGSZ(a0)
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REG_S s3, SC_REGS+S3*REGSZ(a0)
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REG_S s4, SC_REGS+S4*REGSZ(a0)
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REG_S s5, SC_REGS+S5*REGSZ(a0)
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REG_S s6, SC_REGS+S6*REGSZ(a0)
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REG_S s7, SC_REGS+S7*REGSZ(a0)
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REG_S s8, SC_REGS+S8*REGSZ(a0)
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REG_L v0, GPOFF(sp)
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REG_S v0, SC_REGS+GP*REGSZ(a0)
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PTR_ADDU v0, sp, FRAMESZ
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REG_S v0, SC_REGS+SP*REGSZ(a0)
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#if !defined(SOFTFLOAT)
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li v0, 1 # be nice if we could tell
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REG_S v0, SC_FPUSED(a0) # sc_fpused = 1
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cfc1 v0, $31
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#if _MIPS_FPSET == 32
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FPREG64_S($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0)
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FPREG64_S($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0)
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FPREG64_S($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0)
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FPREG64_S($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0)
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FPREG64_S($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0)
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FPREG64_S($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0)
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FPREG64_S($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
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FPREG64_S($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
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FPREG64_S($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
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FPREG64_S($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
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FPREG64_S($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
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FPREG64_S($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
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#else
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swc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
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swc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
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swc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
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swc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
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swc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
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swc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
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swc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
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swc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
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swc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
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swc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
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swc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
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swc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
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#endif
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REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
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#endif /* !SOFTFLOAT */
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move v0, zero
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RESTORE_GP64
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PTR_ADDU sp, FRAMESZ
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j ra
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botch:
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jal longjmperror
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jal abort
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RESTORE_GP64
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PTR_ADDU sp, FRAMESZ
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END(setjmp)
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LEAF(longjmp, FRAMESZ)
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PTR_SUBU sp, FRAMESZ
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SETUP_GP64(GPOFF, longjmp)
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SAVE_GP(GPOFF)
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.set reorder
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sw a1, A1OFF(sp)
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sw a0, A0OFF(sp)
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lw a0, SC_MASK(a0)
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jal sigsetmask
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lw a0, A0OFF(sp)
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lw a1, A1OFF(sp)
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.set noreorder
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REG_L v0, SC_REGS+ZERO*REGSZ(a0)
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bne v0, 0xACEDBADE, botch # jump if error
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REG_L ra, SC_PC(a0)
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REG_L s0, SC_REGS+S0*REGSZ(a0)
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REG_L s1, SC_REGS+S1*REGSZ(a0)
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REG_L s2, SC_REGS+S2*REGSZ(a0)
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REG_L s3, SC_REGS+S3*REGSZ(a0)
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REG_L s4, SC_REGS+S4*REGSZ(a0)
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REG_L s5, SC_REGS+S5*REGSZ(a0)
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REG_L s6, SC_REGS+S6*REGSZ(a0)
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REG_L s7, SC_REGS+S7*REGSZ(a0)
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REG_L s8, SC_REGS+S8*REGSZ(a0)
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REG_L gp, SC_REGS+GP*REGSZ(a0)
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REG_L sp, SC_REGS+SP*REGSZ(a0)
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#if !defined(SOFTFLOAT)
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REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
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ctc1 v0, $31
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#if _MIPS_FPSET == 32
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FPREG64_L($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0)
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FPREG64_L($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0)
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FPREG64_L($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0)
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FPREG64_L($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0)
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FPREG64_L($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0)
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FPREG64_L($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0)
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FPREG64_L($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
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FPREG64_L($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
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FPREG64_L($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
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FPREG64_L($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
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FPREG64_L($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
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FPREG64_L($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
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#else
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lwc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
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lwc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
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lwc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
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lwc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
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lwc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
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lwc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
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lwc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
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lwc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
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lwc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
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lwc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
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lwc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
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lwc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
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#endif
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#endif /* !SOFTFLOAT */
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bne a1, zero, 1f
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nop
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li a1, 1 # never return 0!
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1:
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j ra
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move v0, a1
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END(longjmp)
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