845c778fa6
This patch changes the domain that the memory barrier operates on. Assumes that the scope of bionic_atomic_barrier() does not include device memory, memory shared with the GPU or any other memory external to the processor cluster. Change-Id: I291e741c98a64c86f3a3cf99811bbf1e714ac9aa Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BIONIC_ATOMIC_ARM_H
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#define BIONIC_ATOMIC_ARM_H
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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__asm__ __volatile__ ( "dmb ish" : : : "memory" );
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#else
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/* A simple compiler barrier. */
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__asm__ __volatile__ ( "" : : : "memory" );
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#endif
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}
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/* Compare-and-swap, without any explicit barriers. Note that this function
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* returns 0 on success, and 1 on failure. The opposite convention is typically
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* used on other platforms.
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*/
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__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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"ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"teq %0, %4\n"
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#ifdef __thumb2__
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"it eq\n"
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#endif
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"strexeq %1, %5, [%3]"
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: "=&r" (prev), "=&r" (status), "+m"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev != old_value;
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}
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/* Swap, without any explicit barriers. */
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__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t* ptr) {
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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"ldrex %0, [%3]\n"
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"strex %1, %4, [%3]"
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: "=&r" (prev), "=&r" (status), "+m" (*ptr)
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: "r" (ptr), "r" (new_value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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/* Atomic decrement, without explicit barriers. */
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__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
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int32_t prev, tmp, status;
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do {
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__asm__ __volatile__ (
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"ldrex %0, [%4]\n"
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"sub %1, %0, #1\n"
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"strex %2, %1, [%4]"
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif /* SYS_ATOMICS_ARM_H */
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