96c1db7b9d
Having WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS every four lines made the headers harder to read, made the diffs much worse each time we upgraded, and wasn't really providing any benefit. Before the next uapi update, let's just stop doing this. Bug: N/A Test: builds, manually inspected files look right Change-Id: Id7088cf750894c9d24950f3d53587fe3156c4f7d
142 lines
4.2 KiB
C
142 lines
4.2 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _UAPI_VC4_DRM_H_
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#define _UAPI_VC4_DRM_H_
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#include "drm.h"
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#ifdef __cplusplus
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#endif
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#define DRM_VC4_SUBMIT_CL 0x00
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#define DRM_VC4_WAIT_SEQNO 0x01
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#define DRM_VC4_WAIT_BO 0x02
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#define DRM_VC4_CREATE_BO 0x03
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#define DRM_VC4_MMAP_BO 0x04
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#define DRM_VC4_CREATE_SHADER_BO 0x05
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#define DRM_VC4_GET_HANG_STATE 0x06
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#define DRM_VC4_GET_PARAM 0x07
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#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
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#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
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#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
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#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
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#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
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#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
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#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
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#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
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struct drm_vc4_submit_rcl_surface {
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__u32 hindex;
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__u32 offset;
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__u16 bits;
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#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
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__u16 flags;
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};
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struct drm_vc4_submit_cl {
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__u64 bin_cl;
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__u64 shader_rec;
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__u64 uniforms;
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__u64 bo_handles;
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__u32 bin_cl_size;
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__u32 shader_rec_size;
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__u32 shader_rec_count;
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__u32 uniforms_size;
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__u32 bo_handle_count;
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__u16 width;
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__u16 height;
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__u8 min_x_tile;
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__u8 min_y_tile;
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__u8 max_x_tile;
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__u8 max_y_tile;
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struct drm_vc4_submit_rcl_surface color_read;
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struct drm_vc4_submit_rcl_surface color_write;
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struct drm_vc4_submit_rcl_surface zs_read;
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struct drm_vc4_submit_rcl_surface zs_write;
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struct drm_vc4_submit_rcl_surface msaa_color_write;
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struct drm_vc4_submit_rcl_surface msaa_zs_write;
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__u32 clear_color[2];
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__u32 clear_z;
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__u8 clear_s;
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__u32 pad : 24;
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#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
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__u32 flags;
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__u64 seqno;
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};
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struct drm_vc4_wait_seqno {
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__u64 seqno;
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__u64 timeout_ns;
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};
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struct drm_vc4_wait_bo {
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__u32 handle;
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__u32 pad;
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__u64 timeout_ns;
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};
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struct drm_vc4_create_bo {
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__u32 size;
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__u32 flags;
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__u32 handle;
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__u32 pad;
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};
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struct drm_vc4_mmap_bo {
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__u32 handle;
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__u32 flags;
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__u64 offset;
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};
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struct drm_vc4_create_shader_bo {
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__u32 size;
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__u32 flags;
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__u64 data;
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__u32 handle;
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__u32 pad;
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};
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struct drm_vc4_get_hang_state_bo {
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__u32 handle;
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__u32 paddr;
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__u32 size;
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__u32 pad;
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};
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struct drm_vc4_get_hang_state {
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__u64 bo;
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__u32 bo_count;
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__u32 start_bin, start_render;
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__u32 ct0ca, ct0ea;
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__u32 ct1ca, ct1ea;
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__u32 ct0cs, ct1cs;
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__u32 ct0ra0, ct1ra0;
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__u32 bpca, bpcs;
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__u32 bpoa, bpos;
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__u32 vpmbase;
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__u32 dbge;
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__u32 fdbgo;
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__u32 fdbgb;
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__u32 fdbgr;
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__u32 fdbgs;
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__u32 errstat;
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__u32 pad[16];
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};
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#define DRM_VC4_PARAM_V3D_IDENT0 0
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#define DRM_VC4_PARAM_V3D_IDENT1 1
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#define DRM_VC4_PARAM_V3D_IDENT2 2
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#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
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#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
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#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
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struct drm_vc4_get_param {
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__u32 param;
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__u32 pad;
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__u64 value;
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};
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#ifdef __cplusplus
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#endif
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#endif
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