7e4fa56099
This adds ARMv8 optimized string handling functions to Bionic. The implementations live in a generic/ directory because there will likely be more CPU specific versions (e.g. Cortex-A53 vs. Cortex-A57) later. These implementations are 50%+ faster on current v8 models. Change-Id: If3adc54a284d9519459b0d4d4390f0cd6ded8786 Signed-off-by: Bernhard Rosenkraenzer <Bernhard.Rosenkranzer@linaro.org>
126 lines
4.1 KiB
ArmAsm
126 lines
4.1 KiB
ArmAsm
/* Copyright (c) 2014, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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*/
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#include <private/bionic_asm.h>
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/* Arguments and results. */
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#define srcin x0
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#define len x0
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/* Locals and temporaries. */
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#define src x1
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#define data1 x2
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#define data2 x3
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#define data2a x4
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#define has_nul1 x5
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#define has_nul2 x6
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#define tmp1 x7
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#define tmp2 x8
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#define tmp3 x9
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#define tmp4 x10
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#define zeroones x11
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#define pos x12
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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/* Start of critial section -- keep to one 64Byte cache line. */
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ENTRY(strlen)
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mov zeroones, #REP8_01
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bic src, srcin, #15
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ands tmp1, srcin, #15
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b.ne .Lmisaligned
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/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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can be done in parallel across the entire word. */
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/* The inner loop deals with two Dwords at a time. This has a
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slightly higher start-up cost, but we should win quite quickly,
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especially on cores with a high number of issue slots per
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cycle, as we get much better parallelism out of the operations. */
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.Lloop:
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ldp data1, data2, [src], #16
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.Lrealigned:
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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bic has_nul1, tmp1, tmp2
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bics has_nul2, tmp3, tmp4
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ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */
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b.eq .Lloop
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/* End of critical section -- keep to one 64Byte cache line. */
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sub len, src, srcin
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cbz has_nul1, .Lnul_in_data2
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#ifdef __AARCH64EB__
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mov data2, data1
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#endif
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sub len, len, #8
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mov has_nul2, has_nul1
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.Lnul_in_data2:
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#ifdef __AARCH64EB__
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/* For big-endian, carry propagation (if the final byte in the
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string is 0x01) means we cannot use has_nul directly. The
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easiest way to get the correct byte is to byte-swap the data
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and calculate the syndrome a second time. */
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rev data2, data2
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sub tmp1, data2, zeroones
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orr tmp2, data2, #REP8_7f
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bic has_nul2, tmp1, tmp2
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#endif
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sub len, len, #8
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rev has_nul2, has_nul2
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clz pos, has_nul2
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add len, len, pos, lsr #3 /* Bits to bytes. */
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ret
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.Lmisaligned:
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cmp tmp1, #8
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neg tmp1, tmp1
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ldp data1, data2, [src], #16
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lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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mov tmp2, #~0
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#ifdef __AARCH64EB__
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/* Big-endian. Early bytes are at MSB. */
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lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#else
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/* Little-endian. Early bytes are at LSB. */
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lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#endif
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orr data1, data1, tmp2
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orr data2a, data2, tmp2
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csinv data1, data1, xzr, le
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csel data2, data2, data2a, le
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b .Lrealigned
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END(strlen)
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