7e4fa56099
This adds ARMv8 optimized string handling functions to Bionic. The implementations live in a generic/ directory because there will likely be more CPU specific versions (e.g. Cortex-A53 vs. Cortex-A57) later. These implementations are 50%+ faster on current v8 models. Change-Id: If3adc54a284d9519459b0d4d4390f0cd6ded8786 Signed-off-by: Bernhard Rosenkraenzer <Bernhard.Rosenkranzer@linaro.org>
217 lines
6.7 KiB
ArmAsm
217 lines
6.7 KiB
ArmAsm
/* Copyright (c) 2014, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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*/
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#include <private/bionic_asm.h>
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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/* Parameters and result. */
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#define src1 x0
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#define src2 x1
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#define limit x2
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#define result x0
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/* Internal variables. */
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#define data1 x3
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#define data1w w3
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#define data2 x4
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#define data2w w4
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#define has_nul x5
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#define diff x6
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#define syndrome x7
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#define tmp1 x8
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#define tmp2 x9
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#define tmp3 x10
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#define zeroones x11
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#define pos x12
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#define limit_wd x13
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#define mask x14
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#define endloop x15
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.text
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.p2align 6
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.rep 7
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nop /* Pad so that the loop below fits a cache line. */
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.endr
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ENTRY(strncmp)
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cbz limit, .Lret0
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eor tmp1, src1, src2
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mov zeroones, #REP8_01
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tst tmp1, #7
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b.ne .Lmisaligned8
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ands tmp1, src1, #7
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b.ne .Lmutual_align
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/* Calculate the number of full and partial words -1. */
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sub limit_wd, limit, #1 /* limit != 0, so no underflow. */
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lsr limit_wd, limit_wd, #3 /* Convert to Dwords. */
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/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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can be done in parallel across the entire word. */
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/* Start of performance-critical section -- one 64B cache line. */
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.Lloop_aligned:
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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.Lstart_realigned:
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subs limit_wd, limit_wd, #1
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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eor diff, data1, data2 /* Non-zero if differences found. */
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csinv endloop, diff, xzr, pl /* Last Dword or differences. */
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bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
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ccmp endloop, #0, #0, eq
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b.eq .Lloop_aligned
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/* End of performance-critical section -- one 64B cache line. */
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/* Not reached the limit, must have found the end or a diff. */
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tbz limit_wd, #63, .Lnot_limit
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/* Limit % 8 == 0 => all bytes significant. */
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ands limit, limit, #7
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b.eq .Lnot_limit
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lsl limit, limit, #3 /* Bits -> bytes. */
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mov mask, #~0
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#ifdef __AARCH64EB__
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lsr mask, mask, limit
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#else
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lsl mask, mask, limit
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#endif
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bic data1, data1, mask
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bic data2, data2, mask
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/* Make sure that the NUL byte is marked in the syndrome. */
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orr has_nul, has_nul, mask
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.Lnot_limit:
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orr syndrome, diff, has_nul
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#ifndef __AARCH64EB__
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rev syndrome, syndrome
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rev data1, data1
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/* The MS-non-zero bit of the syndrome marks either the first bit
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that is different, or the top bit of the first zero byte.
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Shifting left now will bring the critical information into the
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top bits. */
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clz pos, syndrome
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rev data2, data2
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lsl data1, data1, pos
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lsl data2, data2, pos
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/* But we need to zero-extend (char is unsigned) the value and then
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perform a signed 32-bit subtraction. */
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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ret
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#else
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/* For big-endian we cannot use the trick with the syndrome value
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as carry-propagation can corrupt the upper bits if the trailing
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bytes in the string contain 0x01. */
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/* However, if there is no NUL byte in the dword, we can generate
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the result directly. We can't just subtract the bytes as the
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MSB might be significant. */
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cbnz has_nul, 1f
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cmp data1, data2
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cset result, ne
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cneg result, result, lo
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ret
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1:
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/* Re-compute the NUL-byte detection, using a byte-reversed value. */
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rev tmp3, data1
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sub tmp1, tmp3, zeroones
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orr tmp2, tmp3, #REP8_7f
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bic has_nul, tmp1, tmp2
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rev has_nul, has_nul
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orr syndrome, diff, has_nul
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clz pos, syndrome
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/* The MS-non-zero bit of the syndrome marks either the first bit
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that is different, or the top bit of the first zero byte.
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Shifting left now will bring the critical information into the
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top bits. */
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lsl data1, data1, pos
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lsl data2, data2, pos
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/* But we need to zero-extend (char is unsigned) the value and then
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perform a signed 32-bit subtraction. */
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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ret
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#endif
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.Lmutual_align:
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/* Sources are mutually aligned, but are not currently at an
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alignment boundary. Round down the addresses and then mask off
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the bytes that precede the start point.
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We also need to adjust the limit calculations, but without
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overflowing if the limit is near ULONG_MAX. */
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bic src1, src1, #7
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bic src2, src2, #7
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ldr data1, [src1], #8
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neg tmp3, tmp1, lsl #3 /* 64 - bits(bytes beyond align). */
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ldr data2, [src2], #8
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mov tmp2, #~0
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sub limit_wd, limit, #1 /* limit != 0, so no underflow. */
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#ifdef __AARCH64EB__
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/* Big-endian. Early bytes are at MSB. */
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lsl tmp2, tmp2, tmp3 /* Shift (tmp1 & 63). */
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#else
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/* Little-endian. Early bytes are at LSB. */
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lsr tmp2, tmp2, tmp3 /* Shift (tmp1 & 63). */
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#endif
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and tmp3, limit_wd, #7
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lsr limit_wd, limit_wd, #3
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/* Adjust the limit. Only low 3 bits used, so overflow irrelevant. */
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add limit, limit, tmp1
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add tmp3, tmp3, tmp1
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orr data1, data1, tmp2
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orr data2, data2, tmp2
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add limit_wd, limit_wd, tmp3, lsr #3
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b .Lstart_realigned
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.Lret0:
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mov result, #0
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ret
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.p2align 6
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.Lmisaligned8:
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sub limit, limit, #1
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1:
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/* Perhaps we can do better than this. */
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ldrb data1w, [src1], #1
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ldrb data2w, [src2], #1
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subs limit, limit, #1
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ccmp data1w, #1, #0, cs /* NZCV = 0b0000. */
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ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
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b.eq 1b
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sub result, data1, data2
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ret
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END(strncmp)
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