No description
dd37251c47
Save and restore floating point registers via 64-bit load/stores when possible. Use assembler's builtin macro ops to generate pairs of 32-bit load/stores on Mips I cpus. Some cpus or FR modes have only 16 even-numbered dp fp regs. This is exposed by _MIPS_FPSET, defined by existing compilers. Change-Id: I7f617a3ffea8da41c402ef3a68ab32c91d3d7622 |
||
---|---|---|
benchmarks | ||
libc | ||
libdl | ||
libm | ||
libstdc++ | ||
linker | ||
tests | ||
.gitignore | ||
ABI-bugs.txt | ||
Android.mk | ||
CleanSpec.mk | ||
HACKING.txt |