fcb877ac4b
Test: Used bionic tests available under bionic/tests folder. Tested for mips32r1/mips32r2/mips64r6 on emulators. Change-Id: I589415ddc496df3f6067ae34cb33ca58b3a1f276 Signed-off-by: Prashant Patil <prashant.patil@imgtec.com>
204 lines
6.2 KiB
C
204 lines
6.2 KiB
C
/*
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* Copyright (c) 2017 Imagination Technologies.
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with
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* the distribution.
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* * Neither the name of Imagination Technologies nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#define op_t unsigned long int
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#if !defined(UNALIGNED_INSTR_SUPPORT)
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/* does target have unaligned lw/ld/ualw/uald instructions? */
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#define UNALIGNED_INSTR_SUPPORT 0
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#if __mips_isa_rev < 6 && !__mips1
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#undef UNALIGNED_INSTR_SUPPORT
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#define UNALIGNED_INSTR_SUPPORT 1
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#endif
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#endif
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#if !defined(HW_UNALIGNED_SUPPORT)
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/* Does target have hardware support for unaligned accesses? */
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#define HW_UNALIGNED_SUPPORT 0
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#if __mips_isa_rev >= 6
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#undef HW_UNALIGNED_SUPPORT
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#define HW_UNALIGNED_SUPPORT 1
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#endif
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#endif
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#if __mips64
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typedef struct
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{
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op_t B0:8, B1:8, B2:8, B3:8, B4:8, B5:8, B6:8, B7:8;
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} bits_t;
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#else
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typedef struct
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{
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op_t B0:8, B1:8, B2:8, B3:8;
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} bits_t;
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#endif
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typedef union
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{
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op_t v;
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bits_t b;
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} bitfields_t;
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#if !HW_UNALIGNED_SUPPORT && UNALIGNED_INSTR_SUPPORT
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/* for MIPS GCC, there are no unaligned builtins - so this struct forces
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the compiler to treat the pointer access as unaligned. */
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struct ulw
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{
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op_t uli;
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} __attribute__ ((packed));
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#endif /* !HW_UNALIGNED_SUPPORT && UNALIGNED_INSTR_SUPPORT */
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#define DO_BYTE(i, ptdst) { \
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*(ptdst+i) = a.b.B##i; \
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if(a.b.B##i == '\0') \
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return ret; \
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}
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#if __mips64
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#define DO_BYTES(val, dst) { \
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bitfields_t a; \
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char *tdst = (char *)(dst); \
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a.v = val; \
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DO_BYTE(0, tdst) \
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DO_BYTE(1, tdst) \
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DO_BYTE(2, tdst) \
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DO_BYTE(3, tdst) \
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DO_BYTE(4, tdst) \
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DO_BYTE(5, tdst) \
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DO_BYTE(6, tdst) \
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DO_BYTE(7, tdst) \
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}
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#else
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#define DO_BYTES(val, dst) { \
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bitfields_t a; \
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char *tdst = (char *)(dst); \
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a.v = val; \
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DO_BYTE(0, tdst) \
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DO_BYTE(1, tdst) \
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DO_BYTE(2, tdst) \
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DO_BYTE(3, tdst) \
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}
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#endif
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#define DO_WORD_ALIGNED(dst, src) { \
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op_t val = *(src); \
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if ((((val - mask_1) & ~val) & mask_128) != 0) { \
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DO_BYTES(val, dst); \
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} else *(dst) = val; \
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}
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#if !HW_UNALIGNED_SUPPORT
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#if UNALIGNED_INSTR_SUPPORT
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#define DO_WORD_UNALIGNED(dst, src) { \
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op_t val = *(src); \
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if ((((val - mask_1) & ~val) & mask_128) != 0) { \
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DO_BYTES(val, dst); \
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} else { \
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struct ulw *a = (struct ulw *)(dst); \
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a->uli = val; \
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} \
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}
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#else
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#define DO_WORD_UNALIGNED(dst, src) { \
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op_t val = *(src); \
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if ((((val - mask_1) & ~val) & mask_128) != 0) { \
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DO_BYTES(val, dst); \
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} else { \
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char *pdst = (char *) dst; \
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const char *psrc = (const char *) src; \
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for (; (*pdst = *psrc) != '\0'; ++psrc, ++pdst); \
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return ret; \
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} \
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}
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#endif /* UNALIGNED_INSTR_SUPPORT */
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#define PROCESS_UNALIGNED_WORDS(a, b) { \
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while (1) { \
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DO_WORD_UNALIGNED(a, b); \
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DO_WORD_UNALIGNED(a + 1, b + 1); \
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DO_WORD_UNALIGNED(a + 2, b + 2); \
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DO_WORD_UNALIGNED(a + 3, b + 3); \
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a += 4; \
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b += 4; \
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} \
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}
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#endif /* HW_UNALIGNED_SUPPORT */
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#define PROCESS_ALIGNED_WORDS(a, b) { \
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while (1) { \
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DO_WORD_ALIGNED(a, b); \
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DO_WORD_ALIGNED(a + 1, b + 1); \
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DO_WORD_ALIGNED(a + 2, b + 2); \
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DO_WORD_ALIGNED(a + 3, b + 3); \
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a += 4; \
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b += 4; \
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} \
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}
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char *
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strcpy (char *to, const char *from) __overloadable
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{
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char *ret = to;
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op_t mask_1, mask_128;
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const op_t *src;
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op_t *dst;
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for (; (*to = *from) != '\0' && ((size_t) from % sizeof (op_t)) != 0; ++from, ++to);
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if(*to != '\0') {
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__asm__ volatile (
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"li %0, 0x01010101 \n\t"
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: "=r" (mask_1)
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);
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#if __mips64
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mask_1 |= mask_1 << 32;
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#endif
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mask_128 = mask_1 << 7;
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src = (const op_t *) from;
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dst = (op_t *) to;
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#if HW_UNALIGNED_SUPPORT
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PROCESS_ALIGNED_WORDS(dst, src);
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#else
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if (((unsigned long) dst) % sizeof (op_t) == 0) {
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PROCESS_ALIGNED_WORDS(dst, src);
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} else {
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PROCESS_UNALIGNED_WORDS(dst, src);
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}
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#endif
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}
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return ret;
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}
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