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7 commits

Author SHA1 Message Date
Duane Sand
6bab974cdc [MIPSR6] Add mips64r6 and mips32r6 targets 
Add mips64r6 target and corresponding mips32r6 target.
Defaults remain as mips64r2 and mips32r2.

Apply -FP64A codegen subsetting to mips32r6 only.
Access FR=0 odd-numbered 32-bit float regs only via
double-prec even-numbered regs, not by single-prec ops.

Change-Id: I1740a6c658304b6c41242be58d68753e6f171658
 2014-07-24 11:19:21 -07:00
Duane Sand
6670e24aed [MIPS] Unite mipsel and mips64el 4.9 gcc toolchains 
Use 4.9 mips64el toolchain for both 64- and 32-bit builds.
Tell ld when 32-bit links are required.
Override 4.9's changed defaults for mips floating point
register use, to get same assembler rules as 4.8 and earlier.

Also: drop unused  soft-fp build targets, cleanout redundant
compiler options, and remove extraneous Android.mk file.

Change-Id: I86f1075266349edb2b08a7709b9f5472d8cfda32
 2014-07-23 14:16:00 -07:00
Pete Delaney
cc41f01490 [MIPS] Add support for MXU instructions for Ingenic builds. 
This enables an Ingenic build to use MXU asm instructions.
MXU support was just recently added:

    ASM: https://android-review.googlesource.com/63701
    GCC: https://android-review.googlesource.com/63702
    BIN: https://android-review.googlesource.com/#/c/63704/

Change-Id: I2b60567a689efa70ec064dfbb0f241a6bc61aed1
Signed-off-by: Pete Delaney <piet.delaney@imgtec.com>
 2013-08-15 18:32:12 -07:00
Raghu Gandham
6faf71647a Do not use -msynci flag for Xburst 4780 cores 
synci does not provide coherency between CPU's on this device

Change-Id: I10e73fa49859e55d018884c6682b5a00b887e0a1
Signed-off-by: Chris Dearman <chris.dearman@imgtec.com>
 2013-06-20 13:29:49 -07:00
Pete Delaney
90ce453470 [MIPS] Disabled madd support for Ingenic Xburst CPUs. 
1. Added xburst ARCH_VARIANT file 'mips32r2-fp-xburst.mk'.
   a) Added -mno-fused-madd GCC option.

2. Removing -mno-fused-madd GCC option for LLVM.


Change-Id: I947a74eb89c05ae321417533c3c40241abc6f965
Signed-off-by: Pete Delaney <piet.delaney@imgtec.com>
 2013-05-20 15:27:20 -07:00
Raghu Gandham
695fee31ad For the current MIPS compiler __builtin___clear_cache() generates synci instruction only with -msynci option 
So, add -msynci to all mips32r2 makefiles. Also add msynci to the list flags not recognized by clang.

Change-Id: I48fd6f2b0cbe80c3cd90f453ced97a2f154f7ad3
Signed-off-by: Rocky Zhang <yan@mips.com>
 2013-02-07 16:07:01 -08:00
Raghu Gandham
06afc1c5ab Support for MIPS Build targets. 
Change-Id: I14c27305298ce36d5c100abf25489275c2269c5f
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Raghu Gandham <raghu@mips.com>
 2012-08-01 11:18:25 -07:00