From 4b350985eb4c62c4589bfd16e54c606060ffdb27 Mon Sep 17 00:00:00 2001 From: Elliott Hughes Date: Wed, 30 Aug 2023 09:37:06 -0700 Subject: [PATCH] riscv64: assume fast unaligned access. We have a CTS test for this, so we may as well let the compiler take advantage! Test: treehugger Change-Id: Icb6dc73be5e6da1155f39ca03245ae6b9d24dfb5 --- cc/config/riscv64_device.go | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/cc/config/riscv64_device.go b/cc/config/riscv64_device.go index e04862209..d5bc7601b 100644 --- a/cc/config/riscv64_device.go +++ b/cc/config/riscv64_device.go @@ -27,6 +27,9 @@ var ( "-Werror=implicit-function-declaration", "-fno-emulated-tls", "-march=rv64gcv_zba_zbb_zbs", + // Equivalent to "-munaligned-access", but our clang doesn't have that yet. + "-Xclang -target-feature -Xclang +unaligned-scalar-mem", + "-Xclang -target-feature -Xclang +unaligned-vector-mem", } riscv64ArchVariantCflags = map[string][]string{} @@ -34,6 +37,9 @@ var ( riscv64Ldflags = []string{ "-Wl,--hash-style=gnu", "-march=rv64gcv_zba_zbb_zbs", + // Equivalent to "-munaligned-access", but our clang doesn't have that yet. + "-Xclang -target-feature -Xclang +unaligned-scalar-mem", + "-Xclang -target-feature -Xclang +unaligned-vector-mem", } riscv64Lldflags = append(riscv64Ldflags,