bee01f7d62
By default clang assumes that on riscv64 jumps are really expensive. That's probably not true for the kind of SoCs we're dealing with, but more importantly (see the bug) it causes clang to do loads from the right hand side of a `&&` before the left hand side has been evaluated. This found one latent bug in libcore, and it doesn't seem like the best use of anyone's time to have to chase similar issues if they're going to be similarly latent for riscv64 when we get clang's default fixed. Bug: https://github.com/google/android-riscv64/issues/124 Test: treehugger Change-Id: I640f1b43ea3d2452366ab86e97a9189fa9f5326c |
||
---|---|---|
.. | ||
Android.bp | ||
arm64_device.go | ||
arm64_linux_host.go | ||
arm_device.go | ||
arm_linux_host.go | ||
bionic.go | ||
cfi_exports.map | ||
clang.go | ||
darwin_host.go | ||
global.go | ||
integer_overflow_blocklist.txt | ||
OWNERS | ||
riscv64_device.go | ||
tidy.go | ||
tidy_test.go | ||
toolchain.go | ||
vndk.go | ||
x86_64_device.go | ||
x86_device.go | ||
x86_linux_bionic_host.go | ||
x86_linux_host.go | ||
x86_windows_host.go |