88 lines
1.6 KiB
Makefile
88 lines
1.6 KiB
Makefile
PREFIX = /usr/local
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TARGETLIBS = libfdt.a
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LIBOBJS = fdt.o fdt_ro.o fdt_wip.o fdt_sw.o
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SOURCE = $(shell find . -maxdepth 1 ! -name version.h -a -name '*.[h]')
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SOURCE += *.c Makefile
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NODEPTARGETS=<clean>
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CPPFLAGS = -I.
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CFLAGS = -Wall -g
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LIBDIR = $(PREFIX)/$(LIB32)
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EXTRA_DIST = \
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README \
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HOWTO \
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LGPL-2.1
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ifdef V
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VECHO = :
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else
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VECHO = echo " "
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ARFLAGS = rc
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.SILENT:
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endif
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DEPFILES = $(LIBOBJS:%.o=%.d)
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all: libs tests
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.PHONY: tests libs
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libs: $(TARGETLIBS)
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tests: tests/all
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tests/%: libs
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$(MAKE) -C tests $*
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check: all
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cd tests; ./run_tests.sh
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checkv: all
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cd tests; ./run_tests.sh -v
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func: all
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cd tests; ./run_tests.sh -t func
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funcv: all
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cd tests; ./run_tests.sh -t func -v
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stress: all
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cd tests; ./run_tests.sh -t stress
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stressv: all
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cd tests; ./run_tests.sh -t stress -v
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%.o: %.c
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@$(VECHO) CC $@
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$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $<
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libfdt.a: $(LIBOBJS)
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@$(VECHO) AR $@
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$(AR) $(ARFLAGS) $@ $^
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%.i: %.c
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@$(VECHO) CPP $@
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$(CC) $(CPPFLAGS) -E $< > $@
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%.s: %.c
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@$(VECHO) CC -S $@
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$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -S $<
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clean:
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@$(VECHO) CLEAN
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rm -f *~ *.o *.so *.a *.d *.i *.s core a.out $(VERSION)
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$(MAKE) -C tests clean
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%.d: %.c
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@$(CC) $(CPPFLAGS) -MM -MT "$*.o $@" $< > $@
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# Workaround: Don't build dependencies for certain targets
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# When the include below is executed, make will use the %.d target above to
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# generate missing files. For certain targets (clean, version.h, etc) we don't
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# need or want these dependency files, so don't include them in this case.
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ifeq (,$(findstring <$(MAKECMDGOALS)>,$(NODEPTARGETS)))
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-include $(DEPFILES)
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endif
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