[MIPS64] add atomic-mips64
Supplied by Broadcom. Change-Id: Ica8f4f6e713623e372a68e1dc11086ceb52516da
This commit is contained in:
Duane Sand
parent
4e26c95a63
commit
84c3e99231
2 changed files with 253 additions and 0 deletions
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@ -51,6 +51,8 @@ extern "C" {
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#include <cutils/atomic-x86.h>
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#elif defined(__x86_64__)
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#include <cutils/atomic-x86_64.h>
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#elif defined(__mips64)
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#include <cutils/atomic-mips64.h>
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#elif defined(__mips__)
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#include <cutils/atomic-mips.h>
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#else
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251
include/cutils/atomic-mips64.h
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251
include/cutils/atomic-mips64.h
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@ -0,0 +1,251 @@
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/*
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* Copyright (C) 2010 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ANDROID_CUTILS_ATOMIC_MIPS64_H
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#define ANDROID_CUTILS_ATOMIC_MIPS64_H
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#include <stdint.h>
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#ifndef ANDROID_ATOMIC_INLINE
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#define ANDROID_ATOMIC_INLINE inline __attribute__((always_inline))
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#endif
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extern ANDROID_ATOMIC_INLINE void android_compiler_barrier(void)
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{
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__asm__ __volatile__ ("" : : : "memory");
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}
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#if ANDROID_SMP == 0
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extern ANDROID_ATOMIC_INLINE void android_memory_barrier(void)
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{
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android_compiler_barrier();
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}
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extern ANDROID_ATOMIC_INLINE void android_memory_store_barrier(void)
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{
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android_compiler_barrier();
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}
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#else
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extern ANDROID_ATOMIC_INLINE void android_memory_barrier(void)
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{
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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extern ANDROID_ATOMIC_INLINE void android_memory_store_barrier(void)
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{
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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#endif
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extern ANDROID_ATOMIC_INLINE
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int32_t android_atomic_acquire_load(volatile const int32_t *ptr)
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{
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int32_t value = *ptr;
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android_memory_barrier();
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return value;
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}
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extern ANDROID_ATOMIC_INLINE
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int64_t android_atomic_acquire_load64(volatile const int64_t *ptr)
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{
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int64_t value = *ptr;
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android_memory_barrier();
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return value;
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}
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extern ANDROID_ATOMIC_INLINE
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int32_t android_atomic_release_load(volatile const int32_t *ptr)
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{
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android_memory_barrier();
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return *ptr;
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}
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extern ANDROID_ATOMIC_INLINE
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int64_t android_atomic_release_load64(volatile const int64_t *ptr)
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{
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android_memory_barrier();
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return *ptr;
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}
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extern ANDROID_ATOMIC_INLINE
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void android_atomic_acquire_store(int32_t value, volatile int32_t *ptr)
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{
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*ptr = value;
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android_memory_barrier();
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}
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extern ANDROID_ATOMIC_INLINE
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void android_atomic_acquire_store64(int64_t value, volatile int64_t *ptr)
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{
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*ptr = value;
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android_memory_barrier();
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}
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extern ANDROID_ATOMIC_INLINE
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void android_atomic_release_store(int32_t value, volatile int32_t *ptr)
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{
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android_memory_barrier();
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*ptr = value;
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}
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extern ANDROID_ATOMIC_INLINE
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void android_atomic_release_store64(int64_t value, volatile int64_t *ptr)
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{
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android_memory_barrier();
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*ptr = value;
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}
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extern ANDROID_ATOMIC_INLINE
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int android_atomic_cas(int32_t old_value, int32_t new_value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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" ll %[prev], (%[ptr])\n"
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" li %[status], 1\n"
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" bne %[prev], %[old], 9f\n"
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" move %[status], %[new_value]\n"
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" sc %[status], (%[ptr])\n"
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"9:\n"
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: [prev] "=&r" (prev), [status] "=&r" (status)
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: [ptr] "r" (ptr), [old] "r" (old_value), [new_value] "r" (new_value)
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);
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} while (__builtin_expect(status == 0, 0));
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return prev != old_value;
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}
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extern ANDROID_ATOMIC_INLINE
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int64_t android_atomic_cas64(int64_t old_value, int64_t new_value,
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volatile int64_t *ptr)
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{
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return __sync_val_compare_and_swap(ptr, old_value, new_value) != old_value;
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}
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extern ANDROID_ATOMIC_INLINE
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int android_atomic_acquire_cas(int32_t old_value,
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int32_t new_value,
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volatile int32_t *ptr)
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{
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int status = android_atomic_cas(old_value, new_value, ptr);
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android_memory_barrier();
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return status;
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}
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extern ANDROID_ATOMIC_INLINE
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int64_t android_atomic_acquire_cas64(int64_t old_value, int64_t new_value,
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volatile int64_t *ptr)
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{
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int status = android_atomic_cas64(old_value, new_value, ptr);
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android_memory_barrier();
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return status;
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}
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extern ANDROID_ATOMIC_INLINE
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int android_atomic_release_cas(int32_t old_value,
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int32_t new_value,
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volatile int32_t *ptr)
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{
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android_memory_barrier();
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return android_atomic_cas(old_value, new_value, ptr);
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}
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extern ANDROID_ATOMIC_INLINE
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int64_t android_atomic_release_cas64(int64_t old_value, int64_t new_value,
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volatile int64_t *ptr)
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{
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android_memory_barrier();
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return android_atomic_cas64(old_value, new_value, ptr);
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}
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extern ANDROID_ATOMIC_INLINE
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int32_t android_atomic_swap(int32_t new_value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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" move %[status], %[new_value]\n"
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" ll %[prev], (%[ptr])\n"
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" sc %[status], (%[ptr])\n"
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: [prev] "=&r" (prev), [status] "=&r" (status)
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: [ptr] "r" (ptr), [new_value] "r" (new_value)
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);
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} while (__builtin_expect(status == 0, 0));
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android_memory_barrier();
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return prev;
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}
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extern ANDROID_ATOMIC_INLINE
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int32_t android_atomic_add(int32_t increment, volatile int32_t *ptr)
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{
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int32_t prev, status;
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android_memory_barrier();
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do {
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__asm__ __volatile__ (
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" ll %[prev], (%[ptr])\n"
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" addu %[status], %[prev], %[inc]\n"
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" sc %[status], (%[ptr])\n"
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: [status] "=&r" (status), [prev] "=&r" (prev)
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: [ptr] "r" (ptr), [inc] "Ir" (increment)
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);
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} while (__builtin_expect(status == 0, 0));
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return prev;
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}
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extern ANDROID_ATOMIC_INLINE int32_t
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android_atomic_inc(volatile int32_t *addr)
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{
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return android_atomic_add(1, addr);
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}
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extern ANDROID_ATOMIC_INLINE int32_t
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android_atomic_dec(volatile int32_t *addr)
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{
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return android_atomic_add(-1, addr);
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}
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extern ANDROID_ATOMIC_INLINE int32_t
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android_atomic_and(int32_t value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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android_memory_barrier();
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do {
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__asm__ __volatile__ (
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" ll %[prev], (%[ptr])\n"
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" and %[status], %[prev], %[value]\n"
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" sc %[status], (%[ptr])\n"
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: [prev] "=&r" (prev), [status] "=&r" (status)
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: [ptr] "r" (ptr), [value] "Ir" (value)
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);
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} while (__builtin_expect(status == 0, 0));
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return prev;
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}
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extern ANDROID_ATOMIC_INLINE int32_t
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android_atomic_or(int32_t value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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android_memory_barrier();
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do {
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__asm__ __volatile__ (
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" ll %[prev], (%[ptr])\n"
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" or %[status], %[prev], %[value]\n"
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" sc %[status], (%[ptr])\n"
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: [prev] "=&r" (prev), [status] "=&r" (status)
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: [ptr] "r" (ptr), [value] "Ir" (value)
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);
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} while (__builtin_expect(status == 0, 0));
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return prev;
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}
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#endif /* ANDROID_CUTILS_ATOMIC_MIPS_H */
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