ARM codegen: Add disassembler, implement return
This program works:
main() { return 42; }
The disassembler was borrowed from codeflinger, and just modified enough to compile
under C++ without warnings.
Implemented gsym
Implemented a hack verison of li, only works for -256..255
Implemented gjmp
This commit is contained in:
Jack Palevich
parent
546b2249ef
commit
a653561097
8 changed files with 1215 additions and 15 deletions
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@ -6,6 +6,7 @@ include $(CLEAR_VARS)
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#
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LOCAL_MODULE:= acc
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LOCAL_SRC_FILES := acc.cpp
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LOCAL_SRC_FILES := acc.cpp disassem.cpp
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LOCAL_MODULE_TAGS := tests
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include $(BUILD_EXECUTABLE)
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144
libacc/acc.cpp
144
libacc/acc.cpp
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@ -31,6 +31,8 @@
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#include <unistd.h>
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#endif
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#include "disassem.h"
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namespace acc {
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class compiler {
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@ -178,6 +180,8 @@ class compiler {
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virtual void adjustStackAfterCall(int l) = 0;
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virtual int disassemble(FILE* out) = 0;
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/* output a symbol and patch all calls to it */
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virtual void gsym(int t) {
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pCodeBuf->gsym(t);
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@ -185,15 +189,20 @@ class compiler {
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virtual int finishCompile() {
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#if defined(__arm__)
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const long base = long(pCodeBuf->getBase());
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const long curr = base + long(pCodeBuf->getSize());
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int err = cacheflush(base, curr, 0);
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return err;
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const long base = long(pCodeBuf->getBase());
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const long curr = base + long(pCodeBuf->getSize());
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int err = cacheflush(base, curr, 0);
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return err;
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#else
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return 0;
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return 0;
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#endif
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}
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/**
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* Adjust relative branches by this amount.
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*/
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virtual int jumpOffset() = 0;
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protected:
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void o(int n) {
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pCodeBuf->o(n);
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@ -217,6 +226,10 @@ class compiler {
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return pCodeBuf->oad(n,t);
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}
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int getBase() {
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return (int) pCodeBuf->getBase();
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}
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int getPC() {
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return pCodeBuf->getPC();
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}
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@ -271,12 +284,19 @@ class compiler {
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/* load immediate value */
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virtual void li(int t) {
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fprintf(stderr, "li(%d);\n", t);
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oad(0xb8, t); /* mov $xx, %eax */
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if (t >= 0 && t < 255) {
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o4(0xE3A00000 + t); // E3A00000 mov r0, #0
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} else if (t >= -256 && t < 0) {
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// mvn means move constant ^ ~0
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o4(0xE3E00001 - t); // E3E00000 mvn r0, #0
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} else {
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error("immediate constant out of range -256..255: %d", t);
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}
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}
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virtual int gjmp(int t) {
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fprintf(stderr, "gjmp(%d);\n", t);
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return psym(0xe9, t);
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return o4(0xEA000000 + encodeAddress(t));
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}
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/* l = 0: je, l == 1: jne */
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@ -397,7 +417,86 @@ class compiler {
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oad(0xc481, l); /* add $xxx, %esp */
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}
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virtual int jumpOffset() {
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return 4;
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}
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/* output a symbol and patch all calls to it */
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virtual void gsym(int t) {
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fprintf(stderr, "gsym(0x%x)\n", t);
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int n;
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int base = getBase();
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int pc = getPC();
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fprintf(stderr, "pc = 0x%x\n", pc);
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while (t) {
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int data = * (int*) t;
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int decodedOffset = ((BRANCH_REL_ADDRESS_MASK & data) << 2);
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if (decodedOffset == 0) {
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n = 0;
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} else {
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n = base + decodedOffset; /* next value */
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}
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*(int *) t = (data & ~BRANCH_REL_ADDRESS_MASK)
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| encodeRelAddress(pc - t - 8);
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t = n;
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}
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}
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virtual int disassemble(FILE* out) {
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disasmOut = out;
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disasm_interface_t di;
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di.di_readword = disassemble_readword;
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di.di_printaddr = disassemble_printaddr;
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di.di_printf = disassemble_printf;
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int base = getBase();
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int pc = getPC();
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for(int i = base; i < pc; i += 4) {
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fprintf(out, "%08x: %08x ", i, *(int*) i);
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::disasm(&di, i, 0);
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}
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return 0;
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}
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private:
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static FILE* disasmOut;
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static u_int
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disassemble_readword(u_int address)
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{
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return(*((u_int *)address));
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}
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static void
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disassemble_printaddr(u_int address)
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{
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fprintf(disasmOut, "0x%08x", address);
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}
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static void
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disassemble_printf(const char *fmt, ...) {
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va_list ap;
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va_start(ap, fmt);
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vfprintf(disasmOut, fmt, ap);
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va_end(ap);
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}
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static const int BRANCH_REL_ADDRESS_MASK = 0x00ffffff;
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/** Encode a relative address that might also be
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* a label.
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*/
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int encodeAddress(int value) {
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int base = getBase();
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if (value >= base && value <= getPC() ) {
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// This is a label, encode it relative to the base.
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value = value - base;
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}
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return encodeRelAddress(value);
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}
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int encodeRelAddress(int value) {
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return BRANCH_REL_ADDRESS_MASK & (value >> 2);
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}
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void error(const char* fmt,...) {
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va_list ap;
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@ -522,6 +621,14 @@ class compiler {
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oad(0xc481, l); /* add $xxx, %esp */
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}
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virtual int jumpOffset() {
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return 5;
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}
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virtual int disassemble(FILE* out) {
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return 1;
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}
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private:
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static const int operatorHelper[];
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@ -896,7 +1003,7 @@ class compiler {
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pGen->callIndirect(l);
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l = l + 4;
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} else {
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pGen->callRelative(n - codeBuf.getPC() - 5); /* call xxx */
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pGen->callRelative(n - codeBuf.getPC() - pGen->jumpOffset()); /* call xxx */
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}
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if (l)
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pGen->adjustStackAfterCall(l);
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@ -935,7 +1042,7 @@ class compiler {
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if (a && l > 8) {
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a = pGen->gtst(t == OP_LOGICAL_OR, a);
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pGen->li(t != OP_LOGICAL_OR);
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pGen->gjmp(5); /* jmp $ + 5 */
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pGen->gjmp(5); /* jmp $ + 5 (sizeof li, FIXME for ARM) */
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pGen->gsym(a);
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pGen->li(t == OP_LOGICAL_OR);
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}
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@ -974,7 +1081,7 @@ class compiler {
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next();
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skip('(');
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if (t == TOK_WHILE) {
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n = codeBuf.getPC();
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n = codeBuf.getPC(); // top of loop, target of "next" iteration
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a = test_expr();
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} else {
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if (tok != ';')
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@ -988,14 +1095,14 @@ class compiler {
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if (tok != ')') {
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t = pGen->gjmp(0);
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expr();
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pGen->gjmp(n - codeBuf.getPC() - 5);
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pGen->gjmp(n - codeBuf.getPC() - pGen->jumpOffset());
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pGen->gsym(t);
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n = t + 4;
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}
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}
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skip(')');
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block((int) &a);
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pGen->gjmp(n - codeBuf.getPC() - 5); /* jmp */
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pGen->gjmp(n - codeBuf.getPC() - pGen->jumpOffset()); /* jmp */
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pGen->gsym(a);
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} else if (tok == '{') {
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next();
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@ -1179,6 +1286,10 @@ public:
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return 0;
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}
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int disassemble(FILE* out) {
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return pGen->disassemble(out);
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}
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};
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const char* compiler::operatorChars =
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@ -1192,6 +1303,8 @@ const char compiler::operatorLevel[] =
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2, 2 /* ~ ! */
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};
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FILE* compiler::ARMCodeGenerator::disasmOut;
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const int compiler::X86CodeGenerator::operatorHelper[] = {
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0x1, // ++
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0xff, // --
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@ -1226,6 +1339,7 @@ int run(acc::compiler& c, int argc, char** argv) {
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int main(int argc, char** argv) {
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bool doDump = false;
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bool doDisassemble = false;
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const char* inFile = NULL;
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const char* outFile = NULL;
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const char* architecture = "arm";
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@ -1251,6 +1365,9 @@ int main(int argc, char** argv) {
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outFile = argv[i + 1];
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i += 1;
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break;
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case 'S':
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doDisassemble = true;
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break;
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default:
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fprintf(stderr, "Unrecognized flag %s\n", arg);
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return 3;
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@ -1281,6 +1398,9 @@ int main(int argc, char** argv) {
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fprintf(stderr, "Compile failed: %d\n", compileResult);
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return 6;
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}
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if (doDisassemble) {
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compiler.disassemble(stderr);
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}
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if (doDump) {
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FILE* save = fopen(outFile, "w");
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if (!save) {
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300
libacc/armreg.h
Normal file
300
libacc/armreg.h
Normal file
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@ -0,0 +1,300 @@
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/* $NetBSD: armreg.h,v 1.28 2003/10/31 16:30:15 scw Exp $ */
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/*-
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* Copyright (c) 1998, 2001 Ben Harris
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD: /repoman/r/ncvs/src/sys/arm/include/armreg.h,v 1.3 2005/11/21 19:06:25 cognet Exp $
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*/
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#ifndef MACHINE_ARMREG_H
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#define MACHINE_ARMREG_H
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#define INSN_SIZE 4
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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#define PSR_MODE 0x0000001f /* mode mask */
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#define PSR_USR26_MODE 0x00000000
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#define PSR_FIQ26_MODE 0x00000001
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#define PSR_IRQ26_MODE 0x00000002
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#define PSR_SVC26_MODE 0x00000003
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#define PSR_USR32_MODE 0x00000010
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#define PSR_FIQ32_MODE 0x00000011
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#define PSR_IRQ32_MODE 0x00000012
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#define PSR_SVC32_MODE 0x00000013
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#define PSR_ABT32_MODE 0x00000017
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#define PSR_UND32_MODE 0x0000001b
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#define PSR_SYS32_MODE 0x0000001f
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#define PSR_32_MODE 0x00000010
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#define PSR_FLAGS 0xf0000000 /* flags */
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#define PSR_C_bit (1 << 29) /* carry */
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/* The high-order byte is always the implementor */
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#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
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#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
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#define CPU_ID_DEC 0x44000000 /* 'D' */
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#define CPU_ID_INTEL 0x69000000 /* 'i' */
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#define CPU_ID_TI 0x54000000 /* 'T' */
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/* How to decide what format the CPUID is in. */
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#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
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#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
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#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
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/* On ARM3 and ARM6, this byte holds the foundry ID. */
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#define CPU_ID_FOUNDRY_MASK 0x00ff0000
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#define CPU_ID_FOUNDRY_VLSI 0x00560000
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/* On ARM7 it holds the architecture and variant (sub-model) */
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#define CPU_ID_7ARCH_MASK 0x00800000
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#define CPU_ID_7ARCH_V3 0x00000000
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#define CPU_ID_7ARCH_V4T 0x00800000
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#define CPU_ID_7VARIANT_MASK 0x007f0000
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/* On more recent ARMs, it does the same, but in a different format */
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#define CPU_ID_ARCH_MASK 0x000f0000
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#define CPU_ID_ARCH_V3 0x00000000
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#define CPU_ID_ARCH_V4 0x00010000
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#define CPU_ID_ARCH_V4T 0x00020000
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#define CPU_ID_ARCH_V5 0x00030000
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#define CPU_ID_ARCH_V5T 0x00040000
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#define CPU_ID_ARCH_V5TE 0x00050000
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#define CPU_ID_VARIANT_MASK 0x00f00000
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/* Next three nybbles are part number */
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#define CPU_ID_PARTNO_MASK 0x0000fff0
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/* Intel XScale has sub fields in part number */
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#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
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#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
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#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
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/* And finally, the revision number. */
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#define CPU_ID_REVISION_MASK 0x0000000f
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/* Individual CPUs are probably best IDed by everything but the revision. */
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#define CPU_ID_CPU_MASK 0xfffffff0
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/* Fake CPU IDs for ARMs without CP15 */
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#define CPU_ID_ARM2 0x41560200
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#define CPU_ID_ARM250 0x41560250
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/* Pre-ARM7 CPUs -- [15:12] == 0 */
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#define CPU_ID_ARM3 0x41560300
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#define CPU_ID_ARM600 0x41560600
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#define CPU_ID_ARM610 0x41560610
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#define CPU_ID_ARM620 0x41560620
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/* ARM7 CPUs -- [15:12] == 7 */
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#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
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#define CPU_ID_ARM710 0x41007100
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#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */
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#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */
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#define CPU_ID_ARM7500FE 0x41077100
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#define CPU_ID_ARM710T 0x41807100
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#define CPU_ID_ARM720T 0x41807200
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#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
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#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
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/* Post-ARM7 CPUs */
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#define CPU_ID_ARM810 0x41018100
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#define CPU_ID_ARM920T 0x41129200
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#define CPU_ID_ARM920T_ALT 0x41009200
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#define CPU_ID_ARM922T 0x41029220
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#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
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#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
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#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
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#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
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#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
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#define CPU_ID_ARM1022ES 0x4105a220
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#define CPU_ID_SA110 0x4401a100
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#define CPU_ID_SA1100 0x4401a110
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#define CPU_ID_TI925T 0x54029250
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#define CPU_ID_SA1110 0x6901b110
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#define CPU_ID_IXP1200 0x6901c120
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#define CPU_ID_80200 0x69052000
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#define CPU_ID_PXA250 0x69052100 /* sans core revision */
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#define CPU_ID_PXA210 0x69052120
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#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
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#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
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#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
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#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
|
||||
#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
|
||||
#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
|
||||
#define CPU_ID_80321_400 0x69052420
|
||||
#define CPU_ID_80321_600 0x69052430
|
||||
#define CPU_ID_80321_400_B0 0x69052c20
|
||||
#define CPU_ID_80321_600_B0 0x69052c30
|
||||
#define CPU_ID_IXP425_533 0x690541c0
|
||||
#define CPU_ID_IXP425_400 0x690541d0
|
||||
#define CPU_ID_IXP425_266 0x690541f0
|
||||
|
||||
/* ARM3-specific coprocessor 15 registers */
|
||||
#define ARM3_CP15_FLUSH 1
|
||||
#define ARM3_CP15_CONTROL 2
|
||||
#define ARM3_CP15_CACHEABLE 3
|
||||
#define ARM3_CP15_UPDATEABLE 4
|
||||
#define ARM3_CP15_DISRUPTIVE 5
|
||||
|
||||
/* ARM3 Control register bits */
|
||||
#define ARM3_CTL_CACHE_ON 0x00000001
|
||||
#define ARM3_CTL_SHARED 0x00000002
|
||||
#define ARM3_CTL_MONITOR 0x00000004
|
||||
|
||||
/*
|
||||
* Post-ARM3 CP15 registers:
|
||||
*
|
||||
* 1 Control register
|
||||
*
|
||||
* 2 Translation Table Base
|
||||
*
|
||||
* 3 Domain Access Control
|
||||
*
|
||||
* 4 Reserved
|
||||
*
|
||||
* 5 Fault Status
|
||||
*
|
||||
* 6 Fault Address
|
||||
*
|
||||
* 7 Cache/write-buffer Control
|
||||
*
|
||||
* 8 TLB Control
|
||||
*
|
||||
* 9 Cache Lockdown
|
||||
*
|
||||
* 10 TLB Lockdown
|
||||
*
|
||||
* 11 Reserved
|
||||
*
|
||||
* 12 Reserved
|
||||
*
|
||||
* 13 Process ID (for FCSE)
|
||||
*
|
||||
* 14 Reserved
|
||||
*
|
||||
* 15 Implementation Dependent
|
||||
*/
|
||||
|
||||
/* Some of the definitions below need cleaning up for V3/V4 architectures */
|
||||
|
||||
/* CPU control register (CP15 register 1) */
|
||||
#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
|
||||
#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
|
||||
#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
|
||||
#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
|
||||
#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
|
||||
#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
|
||||
#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
|
||||
#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
|
||||
#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
|
||||
#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
|
||||
#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
|
||||
#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
|
||||
#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
|
||||
#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
|
||||
#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
|
||||
#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
|
||||
|
||||
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
|
||||
|
||||
/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
|
||||
#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
|
||||
#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
|
||||
#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
|
||||
#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
|
||||
#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
|
||||
#define XSCALE_AUXCTL_MD_MASK 0x00000030
|
||||
|
||||
/* Cache type register definitions */
|
||||
#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
|
||||
#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
|
||||
#define CPU_CT_S (1U << 24) /* split cache */
|
||||
#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
|
||||
|
||||
#define CPU_CT_CTYPE_WT 0 /* write-through */
|
||||
#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
|
||||
#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
|
||||
#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
|
||||
#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
|
||||
|
||||
#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
|
||||
#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
|
||||
#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
|
||||
#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
|
||||
|
||||
/* Fault status register definitions */
|
||||
|
||||
#define FAULT_TYPE_MASK 0x0f
|
||||
#define FAULT_USER 0x10
|
||||
|
||||
#define FAULT_WRTBUF_0 0x00 /* Vector Exception */
|
||||
#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
|
||||
#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
|
||||
#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
|
||||
#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
|
||||
#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
|
||||
#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
|
||||
#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
|
||||
#define FAULT_ALIGN_0 0x01 /* Alignment */
|
||||
#define FAULT_ALIGN_1 0x03 /* Alignment */
|
||||
#define FAULT_TRANS_S 0x05 /* Translation -- Section */
|
||||
#define FAULT_TRANS_P 0x07 /* Translation -- Page */
|
||||
#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
|
||||
#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
|
||||
#define FAULT_PERM_S 0x0d /* Permission -- Section */
|
||||
#define FAULT_PERM_P 0x0f /* Permission -- Page */
|
||||
|
||||
#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
|
||||
|
||||
/*
|
||||
* Address of the vector page, low and high versions.
|
||||
*/
|
||||
#define ARM_VECTORS_LOW 0x00000000U
|
||||
#define ARM_VECTORS_HIGH 0xffff0000U
|
||||
|
||||
/*
|
||||
* ARM Instructions
|
||||
*
|
||||
* 3 3 2 2 2
|
||||
* 1 0 9 8 7 0
|
||||
* +-------+-------------------------------------------------------+
|
||||
* | cond | instruction dependant |
|
||||
* |c c c c| |
|
||||
* +-------+-------------------------------------------------------+
|
||||
*/
|
||||
|
||||
#define INSN_SIZE 4 /* Always 4 bytes */
|
||||
#define INSN_COND_MASK 0xf0000000 /* Condition mask */
|
||||
#define INSN_COND_AL 0xe0000000 /* Always condition */
|
||||
|
||||
#endif /* !MACHINE_ARMREG_H */
|
||||
711
libacc/disassem.cpp
Normal file
711
libacc/disassem.cpp
Normal file
|
|
@ -0,0 +1,711 @@
|
|||
/* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1996 Mark Brinicombe.
|
||||
* Copyright (c) 1996 Brini.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RiscBSD kernel project
|
||||
*
|
||||
* db_disasm.c
|
||||
*
|
||||
* Kernel disassembler
|
||||
*
|
||||
* Created : 10/02/96
|
||||
*
|
||||
* Structured after the sparc/sparc/db_disasm.c by David S. Miller &
|
||||
* Paul Kranenburg
|
||||
*
|
||||
* This code is not complete. Not all instructions are disassembled.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
//__FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/arm/arm/disassem.c,v 1.2 2005/01/05 21:58:47 imp Exp $");
|
||||
#include <sys/param.h>
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
#include "disassem.h"
|
||||
#include "armreg.h"
|
||||
//#include <ddb/ddb.h>
|
||||
|
||||
/*
|
||||
* General instruction format
|
||||
*
|
||||
* insn[cc][mod] [operands]
|
||||
*
|
||||
* Those fields with an uppercase format code indicate that the field
|
||||
* follows directly after the instruction before the separator i.e.
|
||||
* they modify the instruction rather than just being an operand to
|
||||
* the instruction. The only exception is the writeback flag which
|
||||
* follows a operand.
|
||||
*
|
||||
*
|
||||
* 2 - print Operand 2 of a data processing instruction
|
||||
* d - destination register (bits 12-15)
|
||||
* n - n register (bits 16-19)
|
||||
* s - s register (bits 8-11)
|
||||
* o - indirect register rn (bits 16-19) (used by swap)
|
||||
* m - m register (bits 0-3)
|
||||
* a - address operand of ldr/str instruction
|
||||
* e - address operand of ldrh/strh instruction
|
||||
* l - register list for ldm/stm instruction
|
||||
* f - 1st fp operand (register) (bits 12-14)
|
||||
* g - 2nd fp operand (register) (bits 16-18)
|
||||
* h - 3rd fp operand (register/immediate) (bits 0-4)
|
||||
* b - branch address
|
||||
* t - thumb branch address (bits 24, 0-23)
|
||||
* k - breakpoint comment (bits 0-3, 8-19)
|
||||
* X - block transfer type
|
||||
* Y - block transfer type (r13 base)
|
||||
* c - comment field bits(0-23)
|
||||
* p - saved or current status register
|
||||
* F - PSR transfer fields
|
||||
* D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
|
||||
* L - co-processor transfer size
|
||||
* S - set status flag
|
||||
* P - fp precision
|
||||
* Q - fp precision (for ldf/stf)
|
||||
* R - fp rounding
|
||||
* v - co-processor data transfer registers + addressing mode
|
||||
* W - writeback flag
|
||||
* x - instruction in hex
|
||||
* # - co-processor number
|
||||
* y - co-processor data processing registers
|
||||
* z - co-processor register transfer registers
|
||||
*/
|
||||
|
||||
struct arm32_insn {
|
||||
u_int mask;
|
||||
u_int pattern;
|
||||
const char* name;
|
||||
const char* format;
|
||||
};
|
||||
|
||||
static const struct arm32_insn arm32_i[] = {
|
||||
{ 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
|
||||
{ 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
|
||||
{ 0x0f000000, 0x0f000000, "swi", "c" },
|
||||
{ 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
|
||||
{ 0x0f000000, 0x0a000000, "b", "b" },
|
||||
{ 0x0f000000, 0x0b000000, "bl", "b" },
|
||||
{ 0x0fe000f0, 0x00000090, "mul", "Snms" },
|
||||
{ 0x0fe000f0, 0x00200090, "mla", "Snmsd" },
|
||||
{ 0x0fe000f0, 0x00800090, "umull", "Sdnms" },
|
||||
{ 0x0fe000f0, 0x00c00090, "smull", "Sdnms" },
|
||||
{ 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" },
|
||||
{ 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" },
|
||||
{ 0x0d700000, 0x04200000, "strt", "daW" },
|
||||
{ 0x0d700000, 0x04300000, "ldrt", "daW" },
|
||||
{ 0x0d700000, 0x04600000, "strbt", "daW" },
|
||||
{ 0x0d700000, 0x04700000, "ldrbt", "daW" },
|
||||
{ 0x0c500000, 0x04000000, "str", "daW" },
|
||||
{ 0x0c500000, 0x04100000, "ldr", "daW" },
|
||||
{ 0x0c500000, 0x04400000, "strb", "daW" },
|
||||
{ 0x0c500000, 0x04500000, "ldrb", "daW" },
|
||||
{ 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */
|
||||
{ 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */
|
||||
{ 0x0e100000, 0x08000000, "stm", "XnWl" },
|
||||
{ 0x0e100000, 0x08100000, "ldm", "XnWl" },
|
||||
{ 0x0e1000f0, 0x00100090, "ldrb", "deW" },
|
||||
{ 0x0e1000f0, 0x00000090, "strb", "deW" },
|
||||
{ 0x0e1000f0, 0x001000d0, "ldrsb", "deW" },
|
||||
{ 0x0e1000f0, 0x001000b0, "ldrh", "deW" },
|
||||
{ 0x0e1000f0, 0x000000b0, "strh", "deW" },
|
||||
{ 0x0e1000f0, 0x001000f0, "ldrsh", "deW" },
|
||||
{ 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */
|
||||
{ 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */
|
||||
{ 0x0ff00ff0, 0x01000090, "swp", "dmo" },
|
||||
{ 0x0ff00ff0, 0x01400090, "swpb", "dmo" },
|
||||
{ 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */
|
||||
{ 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */
|
||||
{ 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */
|
||||
{ 0x0ffffff0, 0x012fff10, "bx", "m" },
|
||||
{ 0x0fff0ff0, 0x016f0f10, "clz", "dm" },
|
||||
{ 0x0ffffff0, 0x012fff30, "blx", "m" },
|
||||
{ 0xfff000f0, 0xe1200070, "bkpt", "k" },
|
||||
{ 0x0de00000, 0x00000000, "and", "Sdn2" },
|
||||
{ 0x0de00000, 0x00200000, "eor", "Sdn2" },
|
||||
{ 0x0de00000, 0x00400000, "sub", "Sdn2" },
|
||||
{ 0x0de00000, 0x00600000, "rsb", "Sdn2" },
|
||||
{ 0x0de00000, 0x00800000, "add", "Sdn2" },
|
||||
{ 0x0de00000, 0x00a00000, "adc", "Sdn2" },
|
||||
{ 0x0de00000, 0x00c00000, "sbc", "Sdn2" },
|
||||
{ 0x0de00000, 0x00e00000, "rsc", "Sdn2" },
|
||||
{ 0x0df00000, 0x01100000, "tst", "Dn2" },
|
||||
{ 0x0df00000, 0x01300000, "teq", "Dn2" },
|
||||
{ 0x0df00000, 0x01500000, "cmp", "Dn2" },
|
||||
{ 0x0df00000, 0x01700000, "cmn", "Dn2" },
|
||||
{ 0x0de00000, 0x01800000, "orr", "Sdn2" },
|
||||
{ 0x0de00000, 0x01a00000, "mov", "Sd2" },
|
||||
{ 0x0de00000, 0x01c00000, "bic", "Sdn2" },
|
||||
{ 0x0de00000, 0x01e00000, "mvn", "Sd2" },
|
||||
{ 0x0ff08f10, 0x0e000100, "adf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e100100, "muf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e200100, "suf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e600100, "pow", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e900100, "fml", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" },
|
||||
{ 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" },
|
||||
{ 0x0ff08f10, 0x0e008100, "mvf", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e108100, "mnf", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e208100, "abs", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e308100, "rnd", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e408100, "sqt", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e508100, "log", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e608100, "lgn", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e708100, "exp", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e808100, "sin", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0e908100, "cos", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0ea08100, "tan", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0eb08100, "asn", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0ec08100, "acs", "PRfh" },
|
||||
{ 0x0ff08f10, 0x0ed08100, "atn", "PRfh" },
|
||||
{ 0x0f008f10, 0x0e008100, "fpuop", "PRfh" },
|
||||
{ 0x0e100f00, 0x0c000100, "stf", "QLv" },
|
||||
{ 0x0e100f00, 0x0c100100, "ldf", "QLv" },
|
||||
{ 0x0ff00f10, 0x0e000110, "flt", "PRgd" },
|
||||
{ 0x0ff00f10, 0x0e100110, "fix", "PRdh" },
|
||||
{ 0x0ff00f10, 0x0e200110, "wfs", "d" },
|
||||
{ 0x0ff00f10, 0x0e300110, "rfs", "d" },
|
||||
{ 0x0ff00f10, 0x0e400110, "wfc", "d" },
|
||||
{ 0x0ff00f10, 0x0e500110, "rfc", "d" },
|
||||
{ 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" },
|
||||
{ 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" },
|
||||
{ 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" },
|
||||
{ 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" },
|
||||
{ 0xff100010, 0xfe000010, "mcr2", "#z" },
|
||||
{ 0x0f100010, 0x0e000010, "mcr", "#z" },
|
||||
{ 0xff100010, 0xfe100010, "mrc2", "#z" },
|
||||
{ 0x0f100010, 0x0e100010, "mrc", "#z" },
|
||||
{ 0xff000010, 0xfe000000, "cdp2", "#y" },
|
||||
{ 0x0f000010, 0x0e000000, "cdp", "#y" },
|
||||
{ 0xfe100090, 0xfc100000, "ldc2", "L#v" },
|
||||
{ 0x0e100090, 0x0c100000, "ldc", "L#v" },
|
||||
{ 0xfe100090, 0xfc000000, "stc2", "L#v" },
|
||||
{ 0x0e100090, 0x0c000000, "stc", "L#v" },
|
||||
{ 0xf550f000, 0xf550f000, "pld", "ne" },
|
||||
{ 0x0ff00ff0, 0x01000050, "qaad", "dmn" },
|
||||
{ 0x0ff00ff0, 0x01400050, "qdaad", "dmn" },
|
||||
{ 0x0ff00ff0, 0x01600050, "qdsub", "dmn" },
|
||||
{ 0x0ff00ff0, 0x01200050, "dsub", "dmn" },
|
||||
{ 0x0ff000f0, 0x01000080, "smlabb", "nmsd" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x010000a0, "smlatb", "nmsd" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x010000c0, "smlabt", "nmsd" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x010000e0, "smlatt", "nmsd" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x01400080, "smlalbb","ndms" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x014000a0, "smlaltb","ndms" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x014000c0, "smlalbt","ndms" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x014000e0, "smlaltt","ndms" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x01200080, "smlawb", "nmsd" }, // d & n inverted!!
|
||||
{ 0x0ff0f0f0, 0x012000a0, "smulwb","nms" }, // d & n inverted!!
|
||||
{ 0x0ff000f0, 0x012000c0, "smlawt", "nmsd" }, // d & n inverted!!
|
||||
{ 0x0ff0f0f0, 0x012000e0, "smulwt","nms" }, // d & n inverted!!
|
||||
{ 0x0ff0f0f0, 0x01600080, "smulbb","nms" }, // d & n inverted!!
|
||||
{ 0x0ff0f0f0, 0x016000a0, "smultb","nms" }, // d & n inverted!!
|
||||
{ 0x0ff0f0f0, 0x016000c0, "smulbt","nms" }, // d & n inverted!!
|
||||
{ 0x0ff0f0f0, 0x016000e0, "smultt","nms" }, // d & n inverted!!
|
||||
{ 0x00000000, 0x00000000, NULL, NULL }
|
||||
};
|
||||
|
||||
static char const arm32_insn_conditions[][4] = {
|
||||
"eq", "ne", "cs", "cc",
|
||||
"mi", "pl", "vs", "vc",
|
||||
"hi", "ls", "ge", "lt",
|
||||
"gt", "le", "", "nv"
|
||||
};
|
||||
|
||||
static char const insn_block_transfers[][4] = {
|
||||
"da", "ia", "db", "ib"
|
||||
};
|
||||
|
||||
static char const insn_stack_block_transfers[][4] = {
|
||||
"ed", "ea", "fd", "fa"
|
||||
};
|
||||
|
||||
static char const op_shifts[][4] = {
|
||||
"lsl", "lsr", "asr", "ror"
|
||||
};
|
||||
|
||||
static char const insn_fpa_rounding[][2] = {
|
||||
"", "p", "m", "z"
|
||||
};
|
||||
|
||||
static char const insn_fpa_precision[][2] = {
|
||||
"s", "d", "e", "p"
|
||||
};
|
||||
|
||||
static char const insn_fpaconstants[][8] = {
|
||||
"0.0", "1.0", "2.0", "3.0",
|
||||
"4.0", "5.0", "0.5", "10.0"
|
||||
};
|
||||
|
||||
#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f]
|
||||
#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3]
|
||||
#define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3]
|
||||
#define op2_shift(x) op_shifts[(x >> 5) & 3]
|
||||
#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03]
|
||||
#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1]
|
||||
#define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1]
|
||||
#define insn_fpaimm(x) insn_fpaconstants[x & 0x07]
|
||||
|
||||
/* Local prototypes */
|
||||
static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
|
||||
static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
|
||||
static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
|
||||
u_int loc);
|
||||
static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
|
||||
u_int loc);
|
||||
static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
|
||||
u_int loc);
|
||||
static u_int disassemble_readword(u_int address);
|
||||
static void disassemble_printaddr(u_int address);
|
||||
|
||||
u_int
|
||||
disasm(const disasm_interface_t *di, u_int loc, int altfmt)
|
||||
{
|
||||
const struct arm32_insn *i_ptr = &arm32_i[0];
|
||||
|
||||
u_int insn;
|
||||
int matchp;
|
||||
int branch;
|
||||
const char* f_ptr;
|
||||
int fmt;
|
||||
|
||||
fmt = 0;
|
||||
matchp = 0;
|
||||
insn = di->di_readword(loc);
|
||||
|
||||
/* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
|
||||
|
||||
while (i_ptr->name) {
|
||||
if ((insn & i_ptr->mask) == i_ptr->pattern) {
|
||||
matchp = 1;
|
||||
break;
|
||||
}
|
||||
i_ptr++;
|
||||
}
|
||||
|
||||
if (!matchp) {
|
||||
di->di_printf("und%s\t%08x\n", insn_condition(insn), insn);
|
||||
return(loc + INSN_SIZE);
|
||||
}
|
||||
|
||||
/* If instruction forces condition code, don't print it. */
|
||||
if ((i_ptr->mask & 0xf0000000) == 0xf0000000)
|
||||
di->di_printf("%s", i_ptr->name);
|
||||
else
|
||||
di->di_printf("%s%s", i_ptr->name, insn_condition(insn));
|
||||
|
||||
f_ptr = i_ptr->format;
|
||||
|
||||
/* Insert tab if there are no instruction modifiers */
|
||||
|
||||
if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') {
|
||||
++fmt;
|
||||
di->di_printf("\t");
|
||||
}
|
||||
|
||||
while (*f_ptr) {
|
||||
switch (*f_ptr) {
|
||||
/* 2 - print Operand 2 of a data processing instruction */
|
||||
case '2':
|
||||
if (insn & 0x02000000) {
|
||||
int rotate= ((insn >> 7) & 0x1e);
|
||||
|
||||
di->di_printf("#0x%08x",
|
||||
(insn & 0xff) << (32 - rotate) |
|
||||
(insn & 0xff) >> rotate);
|
||||
} else {
|
||||
disasm_register_shift(di, insn);
|
||||
}
|
||||
break;
|
||||
/* d - destination register (bits 12-15) */
|
||||
case 'd':
|
||||
di->di_printf("r%d", ((insn >> 12) & 0x0f));
|
||||
break;
|
||||
/* D - insert 'p' if Rd is R15 */
|
||||
case 'D':
|
||||
if (((insn >> 12) & 0x0f) == 15)
|
||||
di->di_printf("p");
|
||||
break;
|
||||
/* n - n register (bits 16-19) */
|
||||
case 'n':
|
||||
di->di_printf("r%d", ((insn >> 16) & 0x0f));
|
||||
break;
|
||||
/* s - s register (bits 8-11) */
|
||||
case 's':
|
||||
di->di_printf("r%d", ((insn >> 8) & 0x0f));
|
||||
break;
|
||||
/* o - indirect register rn (bits 16-19) (used by swap) */
|
||||
case 'o':
|
||||
di->di_printf("[r%d]", ((insn >> 16) & 0x0f));
|
||||
break;
|
||||
/* m - m register (bits 0-4) */
|
||||
case 'm':
|
||||
di->di_printf("r%d", ((insn >> 0) & 0x0f));
|
||||
break;
|
||||
/* a - address operand of ldr/str instruction */
|
||||
case 'a':
|
||||
disasm_insn_ldrstr(di, insn, loc);
|
||||
break;
|
||||
/* e - address operand of ldrh/strh instruction */
|
||||
case 'e':
|
||||
disasm_insn_ldrhstrh(di, insn, loc);
|
||||
break;
|
||||
/* l - register list for ldm/stm instruction */
|
||||
case 'l':
|
||||
disasm_print_reglist(di, insn);
|
||||
break;
|
||||
/* f - 1st fp operand (register) (bits 12-14) */
|
||||
case 'f':
|
||||
di->di_printf("f%d", (insn >> 12) & 7);
|
||||
break;
|
||||
/* g - 2nd fp operand (register) (bits 16-18) */
|
||||
case 'g':
|
||||
di->di_printf("f%d", (insn >> 16) & 7);
|
||||
break;
|
||||
/* h - 3rd fp operand (register/immediate) (bits 0-4) */
|
||||
case 'h':
|
||||
if (insn & (1 << 3))
|
||||
di->di_printf("#%s", insn_fpaimm(insn));
|
||||
else
|
||||
di->di_printf("f%d", insn & 7);
|
||||
break;
|
||||
/* b - branch address */
|
||||
case 'b':
|
||||
branch = ((insn << 2) & 0x03ffffff);
|
||||
if (branch & 0x02000000)
|
||||
branch |= 0xfc000000;
|
||||
di->di_printaddr(loc + 8 + branch);
|
||||
break;
|
||||
/* t - blx address */
|
||||
case 't':
|
||||
branch = ((insn << 2) & 0x03ffffff) |
|
||||
(insn >> 23 & 0x00000002);
|
||||
if (branch & 0x02000000)
|
||||
branch |= 0xfc000000;
|
||||
di->di_printaddr(loc + 8 + branch);
|
||||
break;
|
||||
/* X - block transfer type */
|
||||
case 'X':
|
||||
di->di_printf("%s", insn_blktrans(insn));
|
||||
break;
|
||||
/* Y - block transfer type (r13 base) */
|
||||
case 'Y':
|
||||
di->di_printf("%s", insn_stkblktrans(insn));
|
||||
break;
|
||||
/* c - comment field bits(0-23) */
|
||||
case 'c':
|
||||
di->di_printf("0x%08x", (insn & 0x00ffffff));
|
||||
break;
|
||||
/* k - breakpoint comment (bits 0-3, 8-19) */
|
||||
case 'k':
|
||||
di->di_printf("0x%04x",
|
||||
(insn & 0x000fff00) >> 4 | (insn & 0x0000000f));
|
||||
break;
|
||||
/* p - saved or current status register */
|
||||
case 'p':
|
||||
if (insn & 0x00400000)
|
||||
di->di_printf("spsr");
|
||||
else
|
||||
di->di_printf("cpsr");
|
||||
break;
|
||||
/* F - PSR transfer fields */
|
||||
case 'F':
|
||||
di->di_printf("_");
|
||||
if (insn & (1 << 16))
|
||||
di->di_printf("c");
|
||||
if (insn & (1 << 17))
|
||||
di->di_printf("x");
|
||||
if (insn & (1 << 18))
|
||||
di->di_printf("s");
|
||||
if (insn & (1 << 19))
|
||||
di->di_printf("f");
|
||||
break;
|
||||
/* B - byte transfer flag */
|
||||
case 'B':
|
||||
if (insn & 0x00400000)
|
||||
di->di_printf("b");
|
||||
break;
|
||||
/* L - co-processor transfer size */
|
||||
case 'L':
|
||||
if (insn & (1 << 22))
|
||||
di->di_printf("l");
|
||||
break;
|
||||
/* S - set status flag */
|
||||
case 'S':
|
||||
if (insn & 0x00100000)
|
||||
di->di_printf("s");
|
||||
break;
|
||||
/* P - fp precision */
|
||||
case 'P':
|
||||
di->di_printf("%s", insn_fpaprec(insn));
|
||||
break;
|
||||
/* Q - fp precision (for ldf/stf) */
|
||||
case 'Q':
|
||||
break;
|
||||
/* R - fp rounding */
|
||||
case 'R':
|
||||
di->di_printf("%s", insn_fparnd(insn));
|
||||
break;
|
||||
/* W - writeback flag */
|
||||
case 'W':
|
||||
if (insn & (1 << 21))
|
||||
di->di_printf("!");
|
||||
break;
|
||||
/* # - co-processor number */
|
||||
case '#':
|
||||
di->di_printf("p%d", (insn >> 8) & 0x0f);
|
||||
break;
|
||||
/* v - co-processor data transfer registers+addressing mode */
|
||||
case 'v':
|
||||
disasm_insn_ldcstc(di, insn, loc);
|
||||
break;
|
||||
/* x - instruction in hex */
|
||||
case 'x':
|
||||
di->di_printf("0x%08x", insn);
|
||||
break;
|
||||
/* y - co-processor data processing registers */
|
||||
case 'y':
|
||||
di->di_printf("%d, ", (insn >> 20) & 0x0f);
|
||||
|
||||
di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f,
|
||||
(insn >> 16) & 0x0f, insn & 0x0f);
|
||||
|
||||
di->di_printf(", %d", (insn >> 5) & 0x07);
|
||||
break;
|
||||
/* z - co-processor register transfer registers */
|
||||
case 'z':
|
||||
di->di_printf("%d, ", (insn >> 21) & 0x07);
|
||||
di->di_printf("r%d, c%d, c%d, %d",
|
||||
(insn >> 12) & 0x0f, (insn >> 16) & 0x0f,
|
||||
insn & 0x0f, (insn >> 5) & 0x07);
|
||||
|
||||
/* if (((insn >> 5) & 0x07) != 0)
|
||||
di->di_printf(", %d", (insn >> 5) & 0x07);*/
|
||||
break;
|
||||
default:
|
||||
di->di_printf("[%c - unknown]", *f_ptr);
|
||||
break;
|
||||
}
|
||||
if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z')
|
||||
++f_ptr;
|
||||
else if (*(++f_ptr)) {
|
||||
++fmt;
|
||||
if (fmt == 1)
|
||||
di->di_printf("\t");
|
||||
else
|
||||
di->di_printf(", ");
|
||||
}
|
||||
};
|
||||
|
||||
di->di_printf("\n");
|
||||
|
||||
return(loc + INSN_SIZE);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
disasm_register_shift(const disasm_interface_t *di, u_int insn)
|
||||
{
|
||||
di->di_printf("r%d", (insn & 0x0f));
|
||||
if ((insn & 0x00000ff0) == 0)
|
||||
;
|
||||
else if ((insn & 0x00000ff0) == 0x00000060)
|
||||
di->di_printf(", rrx");
|
||||
else {
|
||||
if (insn & 0x10)
|
||||
di->di_printf(", %s r%d", op2_shift(insn),
|
||||
(insn >> 8) & 0x0f);
|
||||
else
|
||||
di->di_printf(", %s #%d", op2_shift(insn),
|
||||
(insn >> 7) & 0x1f);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
disasm_print_reglist(const disasm_interface_t *di, u_int insn)
|
||||
{
|
||||
int loop;
|
||||
int start;
|
||||
int comma;
|
||||
|
||||
di->di_printf("{");
|
||||
start = -1;
|
||||
comma = 0;
|
||||
|
||||
for (loop = 0; loop < 17; ++loop) {
|
||||
if (start != -1) {
|
||||
if (loop == 16 || !(insn & (1 << loop))) {
|
||||
if (comma)
|
||||
di->di_printf(", ");
|
||||
else
|
||||
comma = 1;
|
||||
if (start == loop - 1)
|
||||
di->di_printf("r%d", start);
|
||||
else
|
||||
di->di_printf("r%d-r%d", start, loop - 1);
|
||||
start = -1;
|
||||
}
|
||||
} else {
|
||||
if (insn & (1 << loop))
|
||||
start = loop;
|
||||
}
|
||||
}
|
||||
di->di_printf("}");
|
||||
|
||||
if (insn & (1 << 22))
|
||||
di->di_printf("^");
|
||||
}
|
||||
|
||||
static void
|
||||
disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = insn & 0xfff;
|
||||
if ((insn & 0x032f0000) == 0x010f0000) {
|
||||
/* rA = pc, immediate index */
|
||||
if (insn & 0x00800000)
|
||||
loc += offset;
|
||||
else
|
||||
loc -= offset;
|
||||
di->di_printaddr(loc + 8);
|
||||
} else {
|
||||
di->di_printf("[r%d", (insn >> 16) & 0x0f);
|
||||
if ((insn & 0x03000fff) != 0x01000000) {
|
||||
di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
|
||||
if (!(insn & 0x00800000))
|
||||
di->di_printf("-");
|
||||
if (insn & (1 << 25))
|
||||
disasm_register_shift(di, insn);
|
||||
else
|
||||
di->di_printf("#0x%03x", offset);
|
||||
}
|
||||
if (insn & (1 << 24))
|
||||
di->di_printf("]");
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = ((insn & 0xf00) >> 4) | (insn & 0xf);
|
||||
if ((insn & 0x004f0000) == 0x004f0000) {
|
||||
/* rA = pc, immediate index */
|
||||
if (insn & 0x00800000)
|
||||
loc += offset;
|
||||
else
|
||||
loc -= offset;
|
||||
di->di_printaddr(loc + 8);
|
||||
} else {
|
||||
di->di_printf("[r%d", (insn >> 16) & 0x0f);
|
||||
if ((insn & 0x01400f0f) != 0x01400000) {
|
||||
di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
|
||||
if (!(insn & 0x00800000))
|
||||
di->di_printf("-");
|
||||
if (insn & (1 << 22))
|
||||
di->di_printf("#0x%02x", offset);
|
||||
else
|
||||
di->di_printf("r%d", (insn & 0x0f));
|
||||
}
|
||||
if (insn & (1 << 24))
|
||||
di->di_printf("]");
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc)
|
||||
{
|
||||
if (((insn >> 8) & 0xf) == 1)
|
||||
di->di_printf("f%d, ", (insn >> 12) & 0x07);
|
||||
else
|
||||
di->di_printf("c%d, ", (insn >> 12) & 0x0f);
|
||||
|
||||
di->di_printf("[r%d", (insn >> 16) & 0x0f);
|
||||
|
||||
di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
|
||||
|
||||
if (!(insn & (1 << 23)))
|
||||
di->di_printf("-");
|
||||
|
||||
di->di_printf("#0x%03x", (insn & 0xff) << 2);
|
||||
|
||||
if (insn & (1 << 24))
|
||||
di->di_printf("]");
|
||||
|
||||
if (insn & (1 << 21))
|
||||
di->di_printf("!");
|
||||
}
|
||||
|
||||
static u_int
|
||||
disassemble_readword(u_int address)
|
||||
{
|
||||
return(*((u_int *)address));
|
||||
}
|
||||
|
||||
static void
|
||||
disassemble_printaddr(u_int address)
|
||||
{
|
||||
printf("0x%08x", address);
|
||||
}
|
||||
|
||||
static void
|
||||
disassemble_printf(const char *fmt, ...) {
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
vprintf(fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
|
||||
static const disasm_interface_t disassemble_di = {
|
||||
disassemble_readword, disassemble_printaddr, disassemble_printf
|
||||
};
|
||||
|
||||
void
|
||||
disassemble(u_int address)
|
||||
{
|
||||
|
||||
(void)disasm(&disassemble_di, address, 0);
|
||||
}
|
||||
|
||||
/* End of disassem.c */
|
||||
65
libacc/disassem.h
Normal file
65
libacc/disassem.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/* $NetBSD: disassem.h,v 1.4 2001/03/04 04:15:58 matt Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
* Copyright (c) 1997 Causality Limited.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Mark Brinicombe.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Define the interface structure required by the disassembler.
|
||||
*
|
||||
* $FreeBSD: /repoman/r/ncvs/src/sys/arm/include/disassem.h,v 1.2 2005/01/05 21:58:48 imp Exp $
|
||||
*/
|
||||
|
||||
#ifndef ANDROID_MACHINE_DISASSEM_H
|
||||
#define ANDROID_MACHINE_DISASSEM_H
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
u_int (*di_readword)(u_int);
|
||||
void (*di_printaddr)(u_int);
|
||||
void (*di_printf)(const char *, ...);
|
||||
} disasm_interface_t;
|
||||
|
||||
/* Prototypes for callable functions */
|
||||
|
||||
u_int disasm(const disasm_interface_t *, u_int, int);
|
||||
void disassemble(u_int);
|
||||
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !ANDROID_MACHINE_DISASSEM_H */
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
#!/bin/sh
|
||||
g++ acc.cpp -g -ldl -o tests/acc && tests/acc tests/otcc.c -a x86 -d tests/otcc.out && diff tests/otcc.out tests/otcc.out-orig
|
||||
tests/acc tests/simplest.c
|
||||
g++ acc.cpp disassem.cpp -g -ldl -o tests/acc && tests/acc tests/otcc.c -a x86 -d tests/otcc.out && diff tests/otcc.out tests/otcc.out-orig
|
||||
tests/acc -S tests/returnval.c
|
||||
|
|
|
|||
Binary file not shown.
3
libacc/tests/returnval.c
Normal file
3
libacc/tests/returnval.c
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
main() {
|
||||
return 42;
|
||||
}
|
||||
Loading…
Reference in a new issue