I usually call this a "store/store barrier" for maximum clarity, but
the common way of describing it is "store barrier" or "store fence".
This doesn't use "dmb st" yet since we're waiting on the toolchain
update, but it gets the various macros and inline functions in place
so we can use them in the VM.
Bug 3003477
git cherry-pick 2ba5eec3972b4ce46feb677116534fcd3d136e0a
Change-Id: Ifd2d3588be96aa529d490789436cf48c962021ba
This change moves the ARM definitions into GCC extended inline
assembler. In addition, the same set of x86 definitions are now
shared among all x86 targets.
Change-Id: I6e5aa3a413d0af2acbe5d32994983d35a01fdcb3
Added new atomic functions, renamed some old ones. Some #defines have
been added for backward compatibility.
Merged the pre- and post-ARMv6 implementations into a single file.
Renamed the semi-private __android_membar_full_smp to USE_SCREAMING_CAPS
since that's more appropriate for a macro.
Added lots of comments.
Note Mac OS X primitives have not been tested.
Change-Id: If827260750aeb61ad5c2b760e30658e29dbb26f2
Added atomic-inline.h. Added a platform-specific memory barrier call
there.
Added android_atomic_acquire_cmpxchg() and android_atomic_release_store().
Not tested on Mac OS X or SH.
Added memory barrier calls to linux-x86 atomics. Mac OS X has barrier
functions already. sh isn't really SMP-ready. linux-arm needs work
(to be done in a separate change).
Updated the makefile to make the SMP state visible to the code here.
Note that host binaries are NOT built with SMP enabled; while our hosts
are very likely SMP, it's not worth figuring out e.g. whether it's okay
to use the SSE2 mfence instruction or have to use something else. We
haven't had barriers enabled in host tools before, so there's probably
no need to stat now.
Removed quasiatomic 64-bit calls (now part of Dalvik).
Change-Id: I49e5e6c8abe70f304cdedb9d7b8e6e65f8925815
