Intel accidentally made this dead code in 2010 with commit
2bef93cc20, and no one's ever noticed.
Since no one noticing for so long implies that it doesn't matter,
let's just kill the supposedly optimized code.
Change-Id: Id5b37056cb8884c20bfe2db362e19b46f02e337d
Use expected inline behavior with clang.
GCC defaults to -std=gnu90, giving C89 inline semantics with GNU
extensions. Clang defaults to C99. Explicitly use gnu90.
Mark an unused parameter as __unused.
Fix some incorrect casts.
Change-Id: I05b95585d5e3688eda71769b63b6b8a9237bcaf4
CodeCache casts base address to long and then adds size (of type
ssize_t) to get end address. This can cause sign-extension problems.
This patch instead uses simple pointer arithmetic.
Change-Id: Ib71d515a6fd6a7f4762cf974d6cf4eba9a601fa8
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
For now, use generic C code instead of generated mips instructions,
in the same manner as used on x86 and x86_64 targets.
Change-Id: If3607484e0a446a755c62c030b3069d46ab5beb2
ARCH_ARM_HAVE_NEON is only ever defined to true, so test for that.
For the NEON function to be used, the file has to include
machine/cpu-features.h so that __ARM_HAVE_NEON is defined.
Change-Id: I0db196b39c493092415859e009531fcff6fc1e8b
Signed-off-by: Kévin PETIT <kevin.petit@arm.com>
The error condition was not correctly detected: an error was
reported by checking that the index returned by CodeCache::cache
was non-zero. This did not work because this function can return
a positive value on success.
Change-Id: I1f90125ee62ab277b80da4dfb341733cd6e8e86a
Signed-off-by: Kévin PETIT <kevin.petit@arm.com>
cacheflush doesn't exist on LP64 any more, and gcc's
__builtin___clear_cache is better in every way. Use it instead.
Change-Id: Ibbf6facbdefc15b6dda51d014e1c44fb7aa2b17d
See the comment-block at the top of Aarch64Assembler.cpp
for overview on how AArch64 support has been implemented
In addition, this commit contains
[x] AArch64 inline asm versions of gglmul series of
functions and a new unit test bench to test the
functions
[x] Assembly implementations of scanline_col32cb16blend
and scanline_t32cb16blend for AArch64, with unit
test bench
Change-Id: I915cded9e1d39d9a2a70bf8a0394b8a0064d1eb4
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
GGLAssembler assumes addresses to be 32-bit and uses ARM 32-bit
instructions to load/store/manipulate addresses. To support, 64-bit
architectures, following changes has been done
1. ARMAssemblerInterface has been extended to support four new
operations ADDR_LDR, ADDR_STR, ADDR_SUB, ADDR_ADD. Base class
implements these virtual functions to use 32bit equivalent
function. This avoids existing 32-bit Assembler backend
implementations like ARMAssembler and MIPSAssembler from
mapping the new functions to existing equivalent routines.
This also allows 64-bit Architectures like AArch64 to override
the function in their assembler backend implementations.
2. GGLAssembler code (spread over GGLAssembler.cpp, GGLAssembler.h
and texturing.cpp) has been changed to use the new operations
for address operations.
Change-Id: I3d7eace4691e3e47cef737d97ac67ce6ef4fb18d
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
Pixelflinger's code makes assumptions, at certain places,
that pointers can be stored as ints. This patch makes use
of uintptr_t wherever pointers are stored as int or cast
to int.
Change-Id: Ie76f425cbc82ac038a747f77a95bd31774f4a8e8
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
I was fed-up with the constant conflicts in Eclipse
with the "libutils" version.
Also fix a few copyright notices.
Change-Id: I8ffcb845af4b5d0d178f5565f64dfcfbfa27fcd6
With dlmalloc 2.8.6 the compiler pragmas to suppress warnings are not
necessary.
Also fix compiler warning about redefinition of LOG_TAG.
Depends upon: https://android-review.googlesource.com/42351
Change-Id: I50f70be31f4bd994b09083e722759464476c70b3
Remove mspace functionality from cutils.
Directly declare mspace from dlmalloc in code flinger's code cache, and
manage without using morecore.
Depends upon: https://android-review.googlesource.com/41717
Change-Id: If927254febd4414212c690f16509ef2ee1b44b44
This patch adds a dozen more "shortcut" scanline-processing functions
to pixel-flingers. All of them avoid using the JIT for the corresponding
operation (on ARM), or using the generic and _extremely_ slow 'scanline'
function (on x86, where there is no JIT).
The shortcuts were selected by running the system under emulation
(build full_x86-eng, then launch emulator-x86), and correspond to
operations that are in use when using the system's typical UI features.
This makes it much more responsive and amenable to testing most
applications, at least those that don't use OpenGL ES heavily.
Note that HW OpenGLES emulation is under completion and should solve this
problem entirely, though is not there yet.
Change-Id: I9c73ba21ad158d6cc5532fabe7ed2419e00ecb3f
Merge commit '8e0e372a388434a0553810e2b958e59a26a6bd96' into gingerbread-plus-aosp
* commit '8e0e372a388434a0553810e2b958e59a26a6bd96':
Set PROT_EXEC on the whole pixelflinger code cache.
The pointer difference between word pointers is a number
of words, and it needs to be multiplied by the size of a word
to get a proper byte size.
Without this, we tend to see crashes when the code crosses
a page boundary.
Bug: 3026204
Bug: 3097482
Change-Id: I37776d26d5afcdb1da71680de02fbb95e6548371
According to the ARM Architecture Reference Manual, the comment on
STM instruction should be in reverse order.
Change-Id: I4af852a0478798ff7b02ab9c29c68e320ff78696
Signed-off-by: Kan-Ru Chen <kanru@0xlab.org>
Merge commit '4ea1a52b1bbbd6e78c5909c75d773416108f5b84' into gingerbread-plus-aosp
* commit '4ea1a52b1bbbd6e78c5909c75d773416108f5b84':
libpixelflinger: ARMv6 specific objects are not used. Remove.
Merge commit '6090dacd1894429baaf13f7b30b2f6e9e2c1617f' into gingerbread-plus-aosp
* commit '6090dacd1894429baaf13f7b30b2f6e9e2c1617f':
libpixelflinger: Move codeflinger test function to test-opengl-codegen
