Use external/safe-iop to check for overflows on arithmetic
operations.
Also remove an unnecessary copy of Vector/SharedBuffer from
codeflinger and use the copy from libutils instead.
Note that some of the unit tests are somewhat useless due to
test-runner limitations : gtest's ability to filter on abort message
doesn't work when combined with messages formatted by android's logging
system.
bug: 22953624
Change-Id: I46b1ae8ca1f3a010be13aca36a091e76a97a7b70
* Explicitly specify default .align 0.
* Use standard ldmfdlo instruction.
* Before and after gas outputs are identical,
with align 0 sections.
* Objdump showed .text/.data/.bss section alignment
attributes are 2^0 from gas and 2^2 from llvm
assembler. These .S files might be working when
compiled by gas, but llvm assembler's output should
be more correct or conservative.
Change-Id: I4e578dbc8155c0d06d1bbc1c33ec4cc851a18479
pixelflinger should not be used for new projects and should be moved out
of system/core at some point. As the first step, move all its headers
under system/core/libpixelflinger/include and update its Android.mk
files so they're not referring to the absolute system/core path anymore.
Change-Id: Idead273ab2c0450409d770f5402c4dba916192a9
Signed-off-by: Greg Hackmann <ghackmann@google.com>
libagl is now the only remaining pixelflinger client in the Android
tree, and it links with pixelflinger dynamically.
Change-Id: Ic5f8af57a88ceaeb25bf890cd6be8bc5a893fc10
Signed-off-by: Greg Hackmann <ghackmann@google.com>
pixelflinger should not be used for new projects and should be moved out
of system/core at some point. As the first step, move all its headers
under system/core/libpixelflinger/include and update its Android.mk
files so they're not referring to the absolute system/core path anymore.
Change-Id: I7acc3ef5b2e21d8ba6fe939ea8d3ec4c41959591
Signed-off-by: Greg Hackmann <ghackmann@google.com>
Intel accidentally made this dead code in 2010 with commit
2bef93cc20, and no one's ever noticed.
Since no one noticing for so long implies that it doesn't matter,
let's just kill the supposedly optimized code.
Change-Id: Id5b37056cb8884c20bfe2db362e19b46f02e337d
Use expected inline behavior with clang.
GCC defaults to -std=gnu90, giving C89 inline semantics with GNU
extensions. Clang defaults to C99. Explicitly use gnu90.
Mark an unused parameter as __unused.
Fix some incorrect casts.
Change-Id: I05b95585d5e3688eda71769b63b6b8a9237bcaf4
CodeCache casts base address to long and then adds size (of type
ssize_t) to get end address. This can cause sign-extension problems.
This patch instead uses simple pointer arithmetic.
Change-Id: Ib71d515a6fd6a7f4762cf974d6cf4eba9a601fa8
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
For now, use generic C code instead of generated mips instructions,
in the same manner as used on x86 and x86_64 targets.
Change-Id: If3607484e0a446a755c62c030b3069d46ab5beb2
ARCH_ARM_HAVE_NEON is only ever defined to true, so test for that.
For the NEON function to be used, the file has to include
machine/cpu-features.h so that __ARM_HAVE_NEON is defined.
Change-Id: I0db196b39c493092415859e009531fcff6fc1e8b
Signed-off-by: Kévin PETIT <kevin.petit@arm.com>
The error condition was not correctly detected: an error was
reported by checking that the index returned by CodeCache::cache
was non-zero. This did not work because this function can return
a positive value on success.
Change-Id: I1f90125ee62ab277b80da4dfb341733cd6e8e86a
Signed-off-by: Kévin PETIT <kevin.petit@arm.com>
cacheflush doesn't exist on LP64 any more, and gcc's
__builtin___clear_cache is better in every way. Use it instead.
Change-Id: Ibbf6facbdefc15b6dda51d014e1c44fb7aa2b17d
See the comment-block at the top of Aarch64Assembler.cpp
for overview on how AArch64 support has been implemented
In addition, this commit contains
[x] AArch64 inline asm versions of gglmul series of
functions and a new unit test bench to test the
functions
[x] Assembly implementations of scanline_col32cb16blend
and scanline_t32cb16blend for AArch64, with unit
test bench
Change-Id: I915cded9e1d39d9a2a70bf8a0394b8a0064d1eb4
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
GGLAssembler assumes addresses to be 32-bit and uses ARM 32-bit
instructions to load/store/manipulate addresses. To support, 64-bit
architectures, following changes has been done
1. ARMAssemblerInterface has been extended to support four new
operations ADDR_LDR, ADDR_STR, ADDR_SUB, ADDR_ADD. Base class
implements these virtual functions to use 32bit equivalent
function. This avoids existing 32-bit Assembler backend
implementations like ARMAssembler and MIPSAssembler from
mapping the new functions to existing equivalent routines.
This also allows 64-bit Architectures like AArch64 to override
the function in their assembler backend implementations.
2. GGLAssembler code (spread over GGLAssembler.cpp, GGLAssembler.h
and texturing.cpp) has been changed to use the new operations
for address operations.
Change-Id: I3d7eace4691e3e47cef737d97ac67ce6ef4fb18d
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
Pixelflinger's code makes assumptions, at certain places,
that pointers can be stored as ints. This patch makes use
of uintptr_t wherever pointers are stored as int or cast
to int.
Change-Id: Ie76f425cbc82ac038a747f77a95bd31774f4a8e8
Signed-off-by: Ashok Bhat <ashok.bhat@arm.com>
I was fed-up with the constant conflicts in Eclipse
with the "libutils" version.
Also fix a few copyright notices.
Change-Id: I8ffcb845af4b5d0d178f5565f64dfcfbfa27fcd6
With dlmalloc 2.8.6 the compiler pragmas to suppress warnings are not
necessary.
Also fix compiler warning about redefinition of LOG_TAG.
Depends upon: https://android-review.googlesource.com/42351
Change-Id: I50f70be31f4bd994b09083e722759464476c70b3
Remove mspace functionality from cutils.
Directly declare mspace from dlmalloc in code flinger's code cache, and
manage without using morecore.
Depends upon: https://android-review.googlesource.com/41717
Change-Id: If927254febd4414212c690f16509ef2ee1b44b44
