9d88176417
when ONE / ONE_MINUS_SRC_ALPHA blending mode was used, the code wasn't saturating the color component. the reason was that this mode is used for premltiplied alpha blending, however, if used with a non premultiplied source, the color component would wrap. unfortunately, this costs 6 extra cycles per pixels, however... "correctness" prevails. this should not impact the UI since it's using h/w acceleration most of the time it also doesn't impact games which should be using h/w GL. This change will slow the emulator down a bit.
202 lines
4.7 KiB
ArmAsm
202 lines
4.7 KiB
ArmAsm
/* libs/pixelflinger/t32cb16blend.S
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**
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** Copyright 2006, The Android Open Source Project
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**
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** Licensed under the Apache License, Version 2.0 (the "License");
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** you may not use this file except in compliance with the License.
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** You may obtain a copy of the License at
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**
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** http://www.apache.org/licenses/LICENSE-2.0
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**
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** Unless required by applicable law or agreed to in writing, software
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** distributed under the License is distributed on an "AS IS" BASIS,
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** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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** See the License for the specific language governing permissions and
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** limitations under the License.
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*/
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.text
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.align
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.global scanline_t32cb16blend_arm
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/*
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* .macro pixel
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*
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* \DREG is a 32-bit register containing *two* original destination RGB565
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* pixels, with the even one in the low-16 bits, and the odd one in the
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* high 16 bits.
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*
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* \SRC is a 32-bit 0xAABBGGRR pixel value, with pre-multiplied colors.
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*
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* \FB is a target register that will contain the blended pixel values.
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*
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* \ODD is either 0 or 1 and indicates if we're blending the lower or
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* upper 16-bit pixels in DREG into FB
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*
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*
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* clobbered: r6, r7, lr
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*
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*/
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.macro pixel, DREG, SRC, FB, ODD
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// SRC = 0xAABBGGRR
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mov r7, \SRC, lsr #24 // sA
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add r7, r7, r7, lsr #7 // sA + (sA >> 7)
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rsb r7, r7, #0x100 // sA = 0x100 - (sA+(sA>>7))
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1:
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.if \ODD
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// red
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mov lr, \DREG, lsr #(16 + 11)
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smulbb lr, r7, lr
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mov r6, \SRC, lsr #3
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and r6, r6, #0x1F
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add lr, r6, lr, lsr #8
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cmp lr, #0x1F
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orrhs \FB, \FB, #(0x1F<<(16 + 11))
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orrlo \FB, \FB, lr, lsl #(16 + 11)
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// green
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and r6, \DREG, #(0x3F<<(16 + 5))
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smulbt r6, r7, r6
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mov lr, \SRC, lsr #(8+2)
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and lr, lr, #0x3F
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add r6, lr, r6, lsr #(5+8)
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cmp r6, #0x3F
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orrhs \FB, \FB, #(0x3F<<(16 + 5))
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orrlo \FB, \FB, r6, lsl #(16 + 5)
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// blue
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and lr, \DREG, #(0x1F << 16)
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smulbt lr, r7, lr
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mov r6, \SRC, lsr #(8+8+3)
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and r6, r6, #0x1F
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add lr, r6, lr, lsr #8
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cmp lr, #0x1F
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orrhs \FB, \FB, #(0x1F << 16)
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orrlo \FB, \FB, lr, lsl #16
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.else
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// red
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mov lr, \DREG, lsr #11
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and lr, lr, #0x1F
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smulbb lr, r7, lr
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mov r6, \SRC, lsr #3
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and r6, r6, #0x1F
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add lr, r6, lr, lsr #8
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cmp lr, #0x1F
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movhs \FB, #(0x1F<<11)
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movlo \FB, lr, lsl #11
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// green
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and r6, \DREG, #(0x3F<<5)
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smulbb r6, r7, r6
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mov lr, \SRC, lsr #(8+2)
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and lr, lr, #0x3F
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add r6, lr, r6, lsr #(5+8)
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cmp r6, #0x3F
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orrhs \FB, \FB, #(0x3F<<5)
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orrlo \FB, \FB, r6, lsl #5
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// blue
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and lr, \DREG, #0x1F
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smulbb lr, r7, lr
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mov r6, \SRC, lsr #(8+8+3)
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and r6, r6, #0x1F
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add lr, r6, lr, lsr #8
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cmp lr, #0x1F
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orrhs \FB, \FB, #0x1F
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orrlo \FB, \FB, lr
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.endif
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.endm
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// r0: dst ptr
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// r1: src ptr
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// r2: count
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// r3: d
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// r4: s0
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// r5: s1
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// r6: pixel
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// r7: pixel
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// r8: free
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// r9: free
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// r10: free
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// r11: free
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// r12: scratch
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// r14: pixel
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scanline_t32cb16blend_arm:
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stmfd sp!, {r4-r7, lr}
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pld [r0]
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pld [r1]
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// align DST to 32 bits
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tst r0, #0x3
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beq aligned
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subs r2, r2, #1
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ldmlofd sp!, {r4-r7, lr} // return
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bxlo lr
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last:
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ldr r4, [r1], #4
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ldrh r3, [r0]
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pixel r3, r4, r12, 0
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strh r12, [r0], #2
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aligned:
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subs r2, r2, #2
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blo 9f
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// The main loop is unrolled twice and processes 4 pixels
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8: ldmia r1!, {r4, r5}
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// stream the source
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pld [r1, #32]
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add r0, r0, #4
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// it's all zero, skip this pixel
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orrs r3, r4, r5
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beq 7f
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// load the destination
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ldr r3, [r0, #-4]
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// stream the destination
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pld [r0, #32]
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pixel r3, r4, r12, 0
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pixel r3, r5, r12, 1
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// effectively, we're getting write-combining by virtue of the
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// cpu's write-back cache.
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str r12, [r0, #-4]
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// 2nd iterration of the loop, don't stream anything
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subs r2, r2, #2
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movlt r4, r5
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blt 9f
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ldmia r1!, {r4, r5}
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add r0, r0, #4
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orrs r3, r4, r5
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beq 7f
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ldr r3, [r0, #-4]
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pixel r3, r4, r12, 0
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pixel r3, r5, r12, 16
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str r12, [r0, #-4]
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7: subs r2, r2, #2
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bhs 8b
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mov r4, r5
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9: adds r2, r2, #1
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ldmlofd sp!, {r4-r7, lr} // return
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bxlo lr
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b last
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