5ac3927878
We're now using it in contexts that don't have all of the registers available, such as GWP-ASan and soon MTE, so it doesn't make sense to have it be a member function of Regs. Bug: 135772972 Change-Id: I18b104ea0adb78588d7e475d0624cefc701ba52c
305 lines
10 KiB
C++
305 lines
10 KiB
C++
/*
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* Copyright (C) 2017 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdint.h>
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#include <gtest/gtest.h>
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#include <unwindstack/Elf.h>
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#include <unwindstack/ElfInterface.h>
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#include <unwindstack/MapInfo.h>
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#include <unwindstack/RegsArm.h>
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#include <unwindstack/RegsArm64.h>
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#include <unwindstack/RegsX86.h>
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#include <unwindstack/RegsX86_64.h>
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#include <unwindstack/RegsMips.h>
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#include <unwindstack/RegsMips64.h>
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#include "ElfFake.h"
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#include "MemoryFake.h"
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#include "RegsFake.h"
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namespace unwindstack {
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class RegsTest : public ::testing::Test {
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protected:
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void SetUp() override {
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memory_ = new MemoryFake;
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elf_.reset(new ElfFake(memory_));
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elf_interface_ = new ElfInterfaceFake(elf_->memory());
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elf_->FakeSetInterface(elf_interface_);
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}
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ElfInterfaceFake* elf_interface_;
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MemoryFake* memory_;
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std::unique_ptr<ElfFake> elf_;
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};
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TEST_F(RegsTest, regs32) {
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RegsImplFake<uint32_t> regs32(50);
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ASSERT_EQ(50U, regs32.total_regs());
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uint32_t* raw = reinterpret_cast<uint32_t*>(regs32.RawData());
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for (size_t i = 0; i < 50; i++) {
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raw[i] = 0xf0000000 + i;
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}
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regs32.set_pc(0xf0120340);
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regs32.set_sp(0xa0ab0cd0);
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for (size_t i = 0; i < 50; i++) {
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ASSERT_EQ(0xf0000000U + i, regs32[i]) << "Failed comparing register " << i;
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}
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ASSERT_EQ(0xf0120340U, regs32.pc());
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ASSERT_EQ(0xa0ab0cd0U, regs32.sp());
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regs32[32] = 10;
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ASSERT_EQ(10U, regs32[32]);
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}
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TEST_F(RegsTest, regs64) {
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RegsImplFake<uint64_t> regs64(30);
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ASSERT_EQ(30U, regs64.total_regs());
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uint64_t* raw = reinterpret_cast<uint64_t*>(regs64.RawData());
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for (size_t i = 0; i < 30; i++) {
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raw[i] = 0xf123456780000000UL + i;
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}
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regs64.set_pc(0xf123456780102030UL);
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regs64.set_sp(0xa123456780a0b0c0UL);
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for (size_t i = 0; i < 30; i++) {
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ASSERT_EQ(0xf123456780000000U + i, regs64[i]) << "Failed reading register " << i;
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}
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ASSERT_EQ(0xf123456780102030UL, regs64.pc());
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ASSERT_EQ(0xa123456780a0b0c0UL, regs64.sp());
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regs64[8] = 10;
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ASSERT_EQ(10U, regs64[8]);
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}
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TEST_F(RegsTest, rel_pc) {
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EXPECT_EQ(4U, GetPcAdjustment(0x10, elf_.get(), ARCH_ARM64));
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EXPECT_EQ(4U, GetPcAdjustment(0x4, elf_.get(), ARCH_ARM64));
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EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_ARM64));
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EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM64));
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EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM64));
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EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_ARM64));
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EXPECT_EQ(1U, GetPcAdjustment(0x100, elf_.get(), ARCH_X86));
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EXPECT_EQ(1U, GetPcAdjustment(0x2, elf_.get(), ARCH_X86));
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EXPECT_EQ(1U, GetPcAdjustment(0x1, elf_.get(), ARCH_X86));
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EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_X86));
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EXPECT_EQ(1U, GetPcAdjustment(0x100, elf_.get(), ARCH_X86_64));
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EXPECT_EQ(1U, GetPcAdjustment(0x2, elf_.get(), ARCH_X86_64));
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EXPECT_EQ(1U, GetPcAdjustment(0x1, elf_.get(), ARCH_X86_64));
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EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_X86_64));
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EXPECT_EQ(8U, GetPcAdjustment(0x10, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(8U, GetPcAdjustment(0x8, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x7, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x6, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x5, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x4, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_MIPS));
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EXPECT_EQ(8U, GetPcAdjustment(0x10, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(8U, GetPcAdjustment(0x8, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x7, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x6, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x5, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x4, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_MIPS64));
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EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_MIPS64));
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}
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TEST_F(RegsTest, rel_pc_arm) {
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// Check fence posts.
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elf_->FakeSetLoadBias(0);
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EXPECT_EQ(2U, GetPcAdjustment(0x5, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x4, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x3, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM));
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EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM));
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EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_ARM));
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elf_->FakeSetLoadBias(0x100);
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EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0xff, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x105, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x104, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x103, elf_.get(), ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x102, elf_.get(), ARCH_ARM));
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EXPECT_EQ(0U, GetPcAdjustment(0x101, elf_.get(), ARCH_ARM));
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EXPECT_EQ(0U, GetPcAdjustment(0x100, elf_.get(), ARCH_ARM));
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// Check thumb instructions handling.
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elf_->FakeSetLoadBias(0);
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memory_->SetData32(0x2000, 0);
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EXPECT_EQ(2U, GetPcAdjustment(0x2005, elf_.get(), ARCH_ARM));
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memory_->SetData32(0x2000, 0xe000f000);
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EXPECT_EQ(4U, GetPcAdjustment(0x2005, elf_.get(), ARCH_ARM));
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elf_->FakeSetLoadBias(0x400);
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memory_->SetData32(0x2100, 0);
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EXPECT_EQ(2U, GetPcAdjustment(0x2505, elf_.get(), ARCH_ARM));
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memory_->SetData32(0x2100, 0xf111f111);
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EXPECT_EQ(4U, GetPcAdjustment(0x2505, elf_.get(), ARCH_ARM));
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}
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TEST_F(RegsTest, elf_invalid) {
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MapInfo map_info(nullptr, nullptr, 0x1000, 0x2000, 0, 0, "");
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Elf* invalid_elf = new Elf(nullptr);
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map_info.elf.reset(invalid_elf);
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EXPECT_EQ(0x500U, invalid_elf->GetRelPc(0x1500, &map_info));
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EXPECT_EQ(2U, GetPcAdjustment(0x500U, invalid_elf, ARCH_ARM));
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EXPECT_EQ(2U, GetPcAdjustment(0x511U, invalid_elf, ARCH_ARM));
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EXPECT_EQ(0x600U, invalid_elf->GetRelPc(0x1600, &map_info));
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EXPECT_EQ(4U, GetPcAdjustment(0x600U, invalid_elf, ARCH_ARM64));
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EXPECT_EQ(0x700U, invalid_elf->GetRelPc(0x1700, &map_info));
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EXPECT_EQ(1U, GetPcAdjustment(0x700U, invalid_elf, ARCH_X86));
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EXPECT_EQ(0x800U, invalid_elf->GetRelPc(0x1800, &map_info));
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EXPECT_EQ(1U, GetPcAdjustment(0x800U, invalid_elf, ARCH_X86_64));
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EXPECT_EQ(0x900U, invalid_elf->GetRelPc(0x1900, &map_info));
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EXPECT_EQ(8U, GetPcAdjustment(0x900U, invalid_elf, ARCH_MIPS));
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EXPECT_EQ(0xa00U, invalid_elf->GetRelPc(0x1a00, &map_info));
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EXPECT_EQ(8U, GetPcAdjustment(0xa00U, invalid_elf, ARCH_MIPS64));
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}
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TEST_F(RegsTest, arm_verify_sp_pc) {
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RegsArm arm;
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uint32_t* regs = reinterpret_cast<uint32_t*>(arm.RawData());
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regs[13] = 0x100;
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regs[15] = 0x200;
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EXPECT_EQ(0x100U, arm.sp());
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EXPECT_EQ(0x200U, arm.pc());
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}
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TEST_F(RegsTest, arm64_verify_sp_pc) {
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RegsArm64 arm64;
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uint64_t* regs = reinterpret_cast<uint64_t*>(arm64.RawData());
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regs[31] = 0xb100000000ULL;
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regs[32] = 0xc200000000ULL;
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EXPECT_EQ(0xb100000000U, arm64.sp());
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EXPECT_EQ(0xc200000000U, arm64.pc());
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}
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TEST_F(RegsTest, x86_verify_sp_pc) {
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RegsX86 x86;
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uint32_t* regs = reinterpret_cast<uint32_t*>(x86.RawData());
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regs[4] = 0x23450000;
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regs[8] = 0xabcd0000;
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EXPECT_EQ(0x23450000U, x86.sp());
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EXPECT_EQ(0xabcd0000U, x86.pc());
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}
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TEST_F(RegsTest, x86_64_verify_sp_pc) {
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RegsX86_64 x86_64;
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uint64_t* regs = reinterpret_cast<uint64_t*>(x86_64.RawData());
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regs[7] = 0x1200000000ULL;
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regs[16] = 0x4900000000ULL;
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EXPECT_EQ(0x1200000000U, x86_64.sp());
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EXPECT_EQ(0x4900000000U, x86_64.pc());
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}
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TEST_F(RegsTest, mips_verify_sp_pc) {
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RegsMips mips;
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uint32_t* regs = reinterpret_cast<uint32_t*>(mips.RawData());
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regs[29] = 0x100;
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regs[32] = 0x200;
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EXPECT_EQ(0x100U, mips.sp());
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EXPECT_EQ(0x200U, mips.pc());
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}
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TEST_F(RegsTest, mips64_verify_sp_pc) {
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RegsMips64 mips64;
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uint64_t* regs = reinterpret_cast<uint64_t*>(mips64.RawData());
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regs[29] = 0xb100000000ULL;
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regs[32] = 0xc200000000ULL;
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EXPECT_EQ(0xb100000000U, mips64.sp());
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EXPECT_EQ(0xc200000000U, mips64.pc());
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}
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TEST_F(RegsTest, machine_type) {
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RegsArm arm_regs;
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EXPECT_EQ(ARCH_ARM, arm_regs.Arch());
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RegsArm64 arm64_regs;
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EXPECT_EQ(ARCH_ARM64, arm64_regs.Arch());
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RegsX86 x86_regs;
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EXPECT_EQ(ARCH_X86, x86_regs.Arch());
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RegsX86_64 x86_64_regs;
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EXPECT_EQ(ARCH_X86_64, x86_64_regs.Arch());
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RegsMips mips_regs;
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EXPECT_EQ(ARCH_MIPS, mips_regs.Arch());
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RegsMips64 mips64_regs;
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EXPECT_EQ(ARCH_MIPS64, mips64_regs.Arch());
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}
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template <typename RegisterType>
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void clone_test(Regs* regs) {
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RegisterType* register_values = reinterpret_cast<RegisterType*>(regs->RawData());
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int num_regs = regs->total_regs();
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for (int i = 0; i < num_regs; ++i) {
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register_values[i] = i;
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}
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std::unique_ptr<Regs> clone(regs->Clone());
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ASSERT_EQ(regs->total_regs(), clone->total_regs());
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RegisterType* clone_values = reinterpret_cast<RegisterType*>(clone->RawData());
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for (int i = 0; i < num_regs; ++i) {
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EXPECT_EQ(register_values[i], clone_values[i]);
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EXPECT_NE(®ister_values[i], &clone_values[i]);
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}
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}
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TEST_F(RegsTest, clone) {
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std::vector<std::unique_ptr<Regs>> regs;
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regs.emplace_back(new RegsArm());
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regs.emplace_back(new RegsArm64());
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regs.emplace_back(new RegsX86());
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regs.emplace_back(new RegsX86_64());
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regs.emplace_back(new RegsMips());
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regs.emplace_back(new RegsMips64());
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for (auto& r : regs) {
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if (r->Is32Bit()) {
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clone_test<uint32_t>(r.get());
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} else {
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clone_test<uint64_t>(r.get());
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}
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}
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}
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} // namespace unwindstack
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