3958f8060a
This cl includes the code to read arm unwind information from a shared library. Bug: 23762183 Test: Passes all unit tests. I can dump the arm unwind information Test: for an arm shared library. Change-Id: I43501ea2eab843b81de8bd5128401dd1971af8d3
686 lines
17 KiB
C++
686 lines
17 KiB
C++
/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <deque>
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#include <string>
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#include <android-base/stringprintf.h>
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#include "ArmExidx.h"
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#include "Log.h"
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#include "Machine.h"
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#include "Memory.h"
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#include "Regs.h"
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void ArmExidx::LogRawData() {
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std::string log_str("Raw Data:");
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for (const uint8_t data : data_) {
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log_str += android::base::StringPrintf(" 0x%02x", data);
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}
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log(log_indent_, log_str.c_str());
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}
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bool ArmExidx::ExtractEntryData(uint32_t entry_offset) {
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data_.clear();
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status_ = ARM_STATUS_NONE;
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if (entry_offset & 1) {
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// The offset needs to be at least two byte aligned.
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status_ = ARM_STATUS_INVALID_ALIGNMENT;
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return false;
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}
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// Each entry is a 32 bit prel31 offset followed by 32 bits
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// of unwind information. If bit 31 of the unwind data is zero,
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// then this is a prel31 offset to the start of the unwind data.
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// If the unwind data is 1, then this is a cant unwind entry.
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// Otherwise, this data is the compact form of the unwind information.
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uint32_t data;
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if (!elf_memory_->Read32(entry_offset + 4, &data)) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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if (data == 1) {
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// This is a CANT UNWIND entry.
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status_ = ARM_STATUS_NO_UNWIND;
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if (log_) {
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log(log_indent_, "Raw Data: 0x00 0x00 0x00 0x01");
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log(log_indent_, "[cantunwind]");
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}
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return false;
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}
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if (data & (1UL << 31)) {
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// This is a compact table entry.
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if ((data >> 24) & 0xf) {
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// This is a non-zero index, this code doesn't support
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// other formats.
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status_ = ARM_STATUS_INVALID_PERSONALITY;
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return false;
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}
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data_.push_back((data >> 16) & 0xff);
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data_.push_back((data >> 8) & 0xff);
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uint8_t last_op = data & 0xff;
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data_.push_back(last_op);
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if (last_op != ARM_OP_FINISH) {
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// If this didn't end with a finish op, add one.
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data_.push_back(ARM_OP_FINISH);
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}
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if (log_) {
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LogRawData();
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}
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return true;
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}
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// Get the address of the ops.
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// Sign extend the data value if necessary.
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int32_t signed_data = static_cast<int32_t>(data << 1) >> 1;
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uint32_t addr = (entry_offset + 4) + signed_data;
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if (!elf_memory_->Read32(addr, &data)) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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size_t num_table_words;
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if (data & (1UL << 31)) {
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// Compact model.
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switch ((data >> 24) & 0xf) {
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case 0:
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num_table_words = 0;
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data_.push_back((data >> 16) & 0xff);
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break;
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case 1:
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case 2:
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num_table_words = (data >> 16) & 0xff;
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addr += 4;
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break;
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default:
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// Only a personality of 0, 1, 2 is valid.
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status_ = ARM_STATUS_INVALID_PERSONALITY;
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return false;
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}
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data_.push_back((data >> 8) & 0xff);
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data_.push_back(data & 0xff);
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} else {
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// Generic model.
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// Skip the personality routine data, it doesn't contain any data
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// needed to decode the unwind information.
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addr += 4;
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if (!elf_memory_->Read32(addr, &data)) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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num_table_words = (data >> 24) & 0xff;
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data_.push_back((data >> 16) & 0xff);
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data_.push_back((data >> 8) & 0xff);
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data_.push_back(data & 0xff);
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addr += 4;
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}
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if (num_table_words > 5) {
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status_ = ARM_STATUS_MALFORMED;
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return false;
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}
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for (size_t i = 0; i < num_table_words; i++) {
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if (!elf_memory_->Read32(addr, &data)) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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data_.push_back((data >> 24) & 0xff);
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data_.push_back((data >> 16) & 0xff);
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data_.push_back((data >> 8) & 0xff);
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data_.push_back(data & 0xff);
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addr += 4;
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}
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if (data_.back() != ARM_OP_FINISH) {
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// If this didn't end with a finish op, add one.
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data_.push_back(ARM_OP_FINISH);
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}
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if (log_) {
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LogRawData();
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}
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return true;
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}
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inline bool ArmExidx::GetByte(uint8_t* byte) {
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if (data_.empty()) {
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status_ = ARM_STATUS_TRUNCATED;
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return false;
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}
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*byte = data_.front();
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data_.pop_front();
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_00(uint8_t byte) {
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assert((byte >> 4) == 0x8);
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uint16_t registers = (byte & 0xf) << 8;
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if (!GetByte(&byte)) {
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return false;
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}
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registers |= byte;
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if (registers == 0) {
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// 10000000 00000000: Refuse to unwind
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if (log_) {
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log(log_indent_, "Refuse to unwind");
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}
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status_ = ARM_STATUS_NO_UNWIND;
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return false;
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}
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// 1000iiii iiiiiiii: Pop up to 12 integer registers under masks {r15-r12}, {r11-r4}
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if (log_) {
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bool add_comma = false;
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std::string msg = "pop {";
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for (size_t i = 0; i < 12; i++) {
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if (registers & (1 << i)) {
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if (add_comma) {
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msg += ", ";
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}
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msg += android::base::StringPrintf("r%zu", i + 4);
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add_comma = true;
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}
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}
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log(log_indent_, "%s}", msg.c_str());
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if (log_skip_execution_) {
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return true;
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}
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}
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registers <<= 4;
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for (size_t reg = 4; reg < 16; reg++) {
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if (registers & (1 << reg)) {
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if (!process_memory_->Read32(cfa_, &(*regs_)[reg])) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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cfa_ += 4;
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}
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}
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// If the sp register is modified, change the cfa value.
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if (registers & (1 << ARM_REG_SP)) {
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cfa_ = (*regs_)[ARM_REG_SP];
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}
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// Indicate if the pc register was set.
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if (registers & (1 << ARM_REG_PC)) {
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pc_set_ = true;
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}
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_01(uint8_t byte) {
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assert((byte >> 4) == 0x9);
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uint8_t bits = byte & 0xf;
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if (bits == 13 || bits == 15) {
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// 10011101: Reserved as prefix for ARM register to register moves
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// 10011111: Reserved as prefix for Intel Wireless MMX register to register moves
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if (log_) {
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log(log_indent_, "[Reserved]");
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}
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status_ = ARM_STATUS_RESERVED;
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return false;
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}
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// 1001nnnn: Set vsp = r[nnnn] (nnnn != 13, 15)
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if (log_) {
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log(log_indent_, "vsp = r%d", bits);
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if (log_skip_execution_) {
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return true;
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}
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}
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// It is impossible for bits to be larger than the total number of
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// arm registers, so don't bother checking if bits is a valid register.
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cfa_ = (*regs_)[bits];
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_10(uint8_t byte) {
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assert((byte >> 4) == 0xa);
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// 10100nnn: Pop r4-r[4+nnn]
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// 10101nnn: Pop r4-r[4+nnn], r14
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if (log_) {
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std::string msg = "pop {r4";
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uint8_t end_reg = byte & 0x7;
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if (end_reg) {
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msg += android::base::StringPrintf("-r%d", 4 + end_reg);
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}
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if (byte & 0x8) {
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log(log_indent_, "%s, r14}", msg.c_str());
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} else {
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log(log_indent_, "%s}", msg.c_str());
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}
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if (log_skip_execution_) {
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return true;
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}
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}
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for (size_t i = 4; i <= 4 + (byte & 0x7); i++) {
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if (!process_memory_->Read32(cfa_, &(*regs_)[i])) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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cfa_ += 4;
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}
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if (byte & 0x8) {
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if (!process_memory_->Read32(cfa_, &(*regs_)[ARM_REG_R14])) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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cfa_ += 4;
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}
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_11_0000() {
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// 10110000: Finish
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if (log_) {
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log(log_indent_, "finish");
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if (log_skip_execution_) {
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status_ = ARM_STATUS_FINISH;
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return false;
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}
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}
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status_ = ARM_STATUS_FINISH;
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return false;
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}
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inline bool ArmExidx::DecodePrefix_10_11_0001() {
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uint8_t byte;
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if (!GetByte(&byte)) {
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return false;
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}
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if (byte == 0) {
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// 10110001 00000000: Spare
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if (log_) {
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log(log_indent_, "Spare");
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}
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status_ = ARM_STATUS_SPARE;
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return false;
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}
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if (byte >> 4) {
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// 10110001 xxxxyyyy: Spare (xxxx != 0000)
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if (log_) {
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log(log_indent_, "Spare");
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}
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status_ = ARM_STATUS_SPARE;
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return false;
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}
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// 10110001 0000iiii: Pop integer registers under mask {r3, r2, r1, r0}
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if (log_) {
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bool add_comma = false;
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std::string msg = "pop {";
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for (size_t i = 0; i < 4; i++) {
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if (byte & (1 << i)) {
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if (add_comma) {
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msg += ", ";
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}
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msg += android::base::StringPrintf("r%zu", i);
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add_comma = true;
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}
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}
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log(log_indent_, "%s}", msg.c_str());
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if (log_skip_execution_) {
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return true;
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}
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}
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for (size_t reg = 0; reg < 4; reg++) {
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if (byte & (1 << reg)) {
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if (!process_memory_->Read32(cfa_, &(*regs_)[reg])) {
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status_ = ARM_STATUS_READ_FAILED;
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return false;
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}
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cfa_ += 4;
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}
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}
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_11_0010() {
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// 10110010 uleb128: vsp = vsp + 0x204 + (uleb128 << 2)
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uint32_t result = 0;
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uint32_t shift = 0;
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uint8_t byte;
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do {
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if (!GetByte(&byte)) {
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return false;
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}
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result |= (byte & 0x7f) << shift;
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shift += 7;
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} while (byte & 0x80);
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result <<= 2;
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if (log_) {
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log(log_indent_, "vsp = vsp + %d", 0x204 + result);
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if (log_skip_execution_) {
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return true;
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}
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}
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cfa_ += 0x204 + result;
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_11_0011() {
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// 10110011 sssscccc: Pop VFP double precision registers D[ssss]-D[ssss+cccc] by FSTMFDX
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uint8_t byte;
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if (!GetByte(&byte)) {
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return false;
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}
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if (log_) {
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uint8_t start_reg = byte >> 4;
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std::string msg = android::base::StringPrintf("pop {d%d", start_reg);
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uint8_t end_reg = start_reg + (byte & 0xf);
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if (end_reg) {
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msg += android::base::StringPrintf("-d%d", end_reg);
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}
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log(log_indent_, "%s}", msg.c_str());
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if (log_skip_execution_) {
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return true;
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}
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}
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cfa_ += (byte & 0xf) * 8 + 12;
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10_11_01nn() {
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// 101101nn: Spare
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if (log_) {
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log(log_indent_, "Spare");
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}
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status_ = ARM_STATUS_SPARE;
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return false;
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}
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inline bool ArmExidx::DecodePrefix_10_11_1nnn(uint8_t byte) {
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assert((byte & ~0x07) == 0xb8);
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// 10111nnn: Pop VFP double-precision registers D[8]-D[8+nnn] by FSTMFDX
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if (log_) {
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std::string msg = "pop {d8";
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uint8_t last_reg = (byte & 0x7);
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if (last_reg) {
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msg += android::base::StringPrintf("-d%d", last_reg + 8);
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}
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log(log_indent_, "%s}", msg.c_str());
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if (log_skip_execution_) {
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return true;
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}
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}
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// Only update the cfa.
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cfa_ += (byte & 0x7) * 8 + 12;
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return true;
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}
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inline bool ArmExidx::DecodePrefix_10(uint8_t byte) {
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assert((byte >> 6) == 0x2);
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switch ((byte >> 4) & 0x3) {
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case 0:
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return DecodePrefix_10_00(byte);
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case 1:
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return DecodePrefix_10_01(byte);
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case 2:
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return DecodePrefix_10_10(byte);
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default:
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switch (byte & 0xf) {
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case 0:
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return DecodePrefix_10_11_0000();
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case 1:
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return DecodePrefix_10_11_0001();
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case 2:
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return DecodePrefix_10_11_0010();
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case 3:
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return DecodePrefix_10_11_0011();
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default:
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if (byte & 0x8) {
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return DecodePrefix_10_11_1nnn(byte);
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} else {
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return DecodePrefix_10_11_01nn();
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}
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}
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}
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}
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inline bool ArmExidx::DecodePrefix_11_000(uint8_t byte) {
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assert((byte & ~0x07) == 0xc0);
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uint8_t bits = byte & 0x7;
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if (bits == 6) {
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if (!GetByte(&byte)) {
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return false;
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}
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// 11000110 sssscccc: Intel Wireless MMX pop wR[ssss]-wR[ssss+cccc]
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if (log_) {
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uint8_t start_reg = byte >> 4;
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std::string msg = android::base::StringPrintf("pop {wR%d", start_reg);
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uint8_t end_reg = byte & 0xf;
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if (end_reg) {
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msg += android::base::StringPrintf("-wR%d", start_reg + end_reg);
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}
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log(log_indent_, "%s}", msg.c_str());
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if (log_skip_execution_) {
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return true;
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}
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}
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// Only update the cfa.
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cfa_ += (byte & 0xf) * 8 + 8;
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} else if (bits == 7) {
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if (!GetByte(&byte)) {
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return false;
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}
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if (byte == 0) {
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// 11000111 00000000: Spare
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if (log_) {
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log(log_indent_, "Spare");
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}
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status_ = ARM_STATUS_SPARE;
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return false;
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} else if ((byte >> 4) == 0) {
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// 11000111 0000iiii: Intel Wireless MMX pop wCGR registers {wCGR0,1,2,3}
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if (log_) {
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bool add_comma = false;
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std::string msg = "pop {";
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for (size_t i = 0; i < 4; i++) {
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if (byte & (1 << i)) {
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if (add_comma) {
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msg += ", ";
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}
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msg += android::base::StringPrintf("wCGR%zu", i);
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add_comma = true;
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}
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}
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log(log_indent_, "%s}", msg.c_str());
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}
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// Only update the cfa.
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cfa_ += __builtin_popcount(byte) * 4;
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} else {
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// 11000111 xxxxyyyy: Spare (xxxx != 0000)
|
|
if (log_) {
|
|
log(log_indent_, "Spare");
|
|
}
|
|
status_ = ARM_STATUS_SPARE;
|
|
return false;
|
|
}
|
|
} else {
|
|
// 11000nnn: Intel Wireless MMX pop wR[10]-wR[10+nnn] (nnn != 6, 7)
|
|
if (log_) {
|
|
std::string msg = "pop {wR10";
|
|
uint8_t nnn = byte & 0x7;
|
|
if (nnn) {
|
|
msg += android::base::StringPrintf("-wR%d", 10 + nnn);
|
|
}
|
|
log(log_indent_, "%s}", msg.c_str());
|
|
if (log_skip_execution_) {
|
|
return true;
|
|
}
|
|
}
|
|
// Only update the cfa.
|
|
cfa_ += (byte & 0x7) * 8 + 8;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
inline bool ArmExidx::DecodePrefix_11_001(uint8_t byte) {
|
|
assert((byte & ~0x07) == 0xc8);
|
|
|
|
uint8_t bits = byte & 0x7;
|
|
if (bits == 0) {
|
|
// 11001000 sssscccc: Pop VFP double precision registers D[16+ssss]-D[16+ssss+cccc] by VPUSH
|
|
if (!GetByte(&byte)) {
|
|
return false;
|
|
}
|
|
|
|
if (log_) {
|
|
uint8_t start_reg = byte >> 4;
|
|
std::string msg = android::base::StringPrintf("pop {d%d", 16 + start_reg);
|
|
uint8_t end_reg = byte & 0xf;
|
|
if (end_reg) {
|
|
msg += android::base::StringPrintf("-d%d", 16 + start_reg + end_reg);
|
|
}
|
|
log(log_indent_, "%s}", msg.c_str());
|
|
if (log_skip_execution_) {
|
|
return true;
|
|
}
|
|
}
|
|
// Only update the cfa.
|
|
cfa_ += (byte & 0xf) * 8 + 8;
|
|
} else if (bits == 1) {
|
|
// 11001001 sssscccc: Pop VFP double precision registers D[ssss]-D[ssss+cccc] by VPUSH
|
|
if (!GetByte(&byte)) {
|
|
return false;
|
|
}
|
|
|
|
if (log_) {
|
|
uint8_t start_reg = byte >> 4;
|
|
std::string msg = android::base::StringPrintf("pop {d%d", start_reg);
|
|
uint8_t end_reg = byte & 0xf;
|
|
if (end_reg) {
|
|
msg += android::base::StringPrintf("-d%d", start_reg + end_reg);
|
|
}
|
|
log(log_indent_, "%s}", msg.c_str());
|
|
if (log_skip_execution_) {
|
|
return true;
|
|
}
|
|
}
|
|
// Only update the cfa.
|
|
cfa_ += (byte & 0xf) * 8 + 8;
|
|
} else {
|
|
// 11001yyy: Spare (yyy != 000, 001)
|
|
if (log_) {
|
|
log(log_indent_, "Spare");
|
|
}
|
|
status_ = ARM_STATUS_SPARE;
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
inline bool ArmExidx::DecodePrefix_11_010(uint8_t byte) {
|
|
assert((byte & ~0x07) == 0xd0);
|
|
|
|
// 11010nnn: Pop VFP double precision registers D[8]-D[8+nnn] by VPUSH
|
|
if (log_) {
|
|
std::string msg = "pop {d8";
|
|
uint8_t end_reg = byte & 0x7;
|
|
if (end_reg) {
|
|
msg += android::base::StringPrintf("-d%d", 8 + end_reg);
|
|
}
|
|
log(log_indent_, "%s}", msg.c_str());
|
|
if (log_skip_execution_) {
|
|
return true;
|
|
}
|
|
}
|
|
cfa_ += (byte & 0x7) * 8 + 8;
|
|
return true;
|
|
}
|
|
|
|
inline bool ArmExidx::DecodePrefix_11(uint8_t byte) {
|
|
assert((byte >> 6) == 0x3);
|
|
|
|
switch ((byte >> 3) & 0x7) {
|
|
case 0:
|
|
return DecodePrefix_11_000(byte);
|
|
case 1:
|
|
return DecodePrefix_11_001(byte);
|
|
case 2:
|
|
return DecodePrefix_11_010(byte);
|
|
default:
|
|
// 11xxxyyy: Spare (xxx != 000, 001, 010)
|
|
if (log_) {
|
|
log(log_indent_, "Spare");
|
|
}
|
|
status_ = ARM_STATUS_SPARE;
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool ArmExidx::Decode() {
|
|
status_ = ARM_STATUS_NONE;
|
|
uint8_t byte;
|
|
if (!GetByte(&byte)) {
|
|
return false;
|
|
}
|
|
|
|
switch (byte >> 6) {
|
|
case 0:
|
|
// 00xxxxxx: vsp = vsp + (xxxxxxx << 2) + 4
|
|
if (log_) {
|
|
log(log_indent_, "vsp = vsp + %d", ((byte & 0x3f) << 2) + 4);
|
|
if (log_skip_execution_) {
|
|
break;
|
|
}
|
|
}
|
|
cfa_ += ((byte & 0x3f) << 2) + 4;
|
|
break;
|
|
case 1:
|
|
// 01xxxxxx: vsp = vsp - (xxxxxxx << 2) + 4
|
|
if (log_) {
|
|
log(log_indent_, "vsp = vsp - %d", ((byte & 0x3f) << 2) + 4);
|
|
if (log_skip_execution_) {
|
|
break;
|
|
}
|
|
}
|
|
cfa_ -= ((byte & 0x3f) << 2) + 4;
|
|
break;
|
|
case 2:
|
|
return DecodePrefix_10(byte);
|
|
default:
|
|
return DecodePrefix_11(byte);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ArmExidx::Eval() {
|
|
pc_set_ = false;
|
|
while (Decode());
|
|
return status_ == ARM_STATUS_FINISH;
|
|
}
|