ac322da69e
Added atomic-inline.h. Added a platform-specific memory barrier call there. Added android_atomic_acquire_cmpxchg() and android_atomic_release_store(). Not tested on Mac OS X or SH. Added memory barrier calls to linux-x86 atomics. Mac OS X has barrier functions already. sh isn't really SMP-ready. linux-arm needs work (to be done in a separate change). Updated the makefile to make the SMP state visible to the code here. Note that host binaries are NOT built with SMP enabled; while our hosts are very likely SMP, it's not worth figuring out e.g. whether it's okay to use the SSE2 mfence instruction or have to use something else. We haven't had barriers enabled in host tools before, so there's probably no need to stat now. Removed quasiatomic 64-bit calls (now part of Dalvik). Change-Id: I49e5e6c8abe70f304cdedb9d7b8e6e65f8925815
188 lines
5.2 KiB
C
188 lines
5.2 KiB
C
/*
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* Copyright (C) 2007 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <cutils/atomic.h>
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#include <cutils/atomic-inline.h>
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#ifdef HAVE_WIN32_THREADS
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#include <windows.h>
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#else
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#include <sched.h>
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#endif
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/*****************************************************************************/
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#if defined(HAVE_MACOSX_IPC)
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#include <libkern/OSAtomic.h>
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void android_atomic_write(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (OSAtomicCompareAndSwap32Barrier(oldValue, value, (int32_t*)addr) == 0);
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}
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int32_t android_atomic_inc(volatile int32_t* addr) {
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return OSAtomicIncrement32Barrier((int32_t*)addr)-1;
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}
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int32_t android_atomic_dec(volatile int32_t* addr) {
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return OSAtomicDecrement32Barrier((int32_t*)addr)+1;
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}
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int32_t android_atomic_add(int32_t value, volatile int32_t* addr) {
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return OSAtomicAdd32Barrier(value, (int32_t*)addr)-value;
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}
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int32_t android_atomic_and(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (OSAtomicCompareAndSwap32Barrier(oldValue, oldValue&value, (int32_t*)addr) == 0);
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return oldValue;
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}
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int32_t android_atomic_or(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (OSAtomicCompareAndSwap32Barrier(oldValue, oldValue|value, (int32_t*)addr) == 0);
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return oldValue;
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}
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int32_t android_atomic_swap(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, value, addr));
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return oldValue;
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}
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int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue, volatile int32_t* addr) {
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/* OS X CAS returns zero on failure; invert to return zero on success */
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return OSAtomicCompareAndSwap32Barrier(oldvalue, newvalue, (int32_t*)addr) == 0;
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}
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int android_atomic_acquire_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr) {
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int result = (OSAtomicCompareAndSwap32(oldvalue, newvalue, (int32_t*)addr) == 0);
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if (!result) {
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/* success, perform barrier */
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OSMemoryBarrier();
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}
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}
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/*****************************************************************************/
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#elif defined(__i386__) || defined(__x86_64__)
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void android_atomic_write(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, value, addr));
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}
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int32_t android_atomic_inc(volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, oldValue+1, addr));
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return oldValue;
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}
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int32_t android_atomic_dec(volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, oldValue-1, addr));
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return oldValue;
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}
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int32_t android_atomic_add(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, oldValue+value, addr));
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return oldValue;
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}
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int32_t android_atomic_and(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, oldValue&value, addr));
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return oldValue;
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}
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int32_t android_atomic_or(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, oldValue|value, addr));
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return oldValue;
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}
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int32_t android_atomic_swap(int32_t value, volatile int32_t* addr) {
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int32_t oldValue;
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do {
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oldValue = *addr;
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} while (android_atomic_cmpxchg(oldValue, value, addr));
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return oldValue;
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}
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int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue, volatile int32_t* addr) {
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android_membar_full();
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int xchg;
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asm volatile
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(
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" lock; cmpxchg %%ecx, (%%edx);"
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" setne %%al;"
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" andl $1, %%eax"
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: "=a" (xchg)
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: "a" (oldvalue), "c" (newvalue), "d" (addr)
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);
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return xchg;
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}
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int android_atomic_acquire_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr) {
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int xchg;
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asm volatile
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(
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" lock; cmpxchg %%ecx, (%%edx);"
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" setne %%al;"
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" andl $1, %%eax"
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: "=a" (xchg)
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: "a" (oldvalue), "c" (newvalue), "d" (addr)
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);
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android_membar_full();
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return xchg;
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}
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/*****************************************************************************/
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#elif __arm__
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// implementation for ARM is in atomic-android-arm.s.
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/*****************************************************************************/
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#elif __sh__
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// implementation for SuperH is in atomic-android-sh.c.
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#else
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#error "Unsupported atomic operations for this platform"
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#endif
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