Each release we're asked to investigate tombstones from code that hasn't
been allowed to run on Android since L. This is just wasting our time,
and clearly the "obviousness" of aborting rather than exiting hasn't ensured
that all app developers rebuild their old binaries. In some cases it seems
like they run them "just in case" and don't care if they fail.
Bug: http://b/34112178
Test: ran libsupervisor.so from com.ss.android.article.news
Change-Id: I8a3f196c4755601a3888281566fbb7b817f01dca
The crash happens because for static executables call to dlopen
results in crash. This change moves dlopen() == nullptr check
from static variable to a functions so that the dlopen crash only
affects tests calling dlopen but not the whole executable.
Also make static tests report crashes to debugerd
Test: run bionic-unit-tests-static (for arm 32 and 64)
Bug: http://b/34129417
Change-Id: I7c4d8caf2a43250234fe24496b1c95eab572769f
Don't allow processes to read the contents of the directory
/dev/__properties__. This is an implementation detail of the properties
system that processes shouldn't be concerned with.
Test: Device boots and no problems reading individual properties.
Test: ls -la /dev/__properties__ fails
Change-Id: I00130fe4529525935654bff91e3cc59253b86e26
For apps targeting pre-O releases print warn about
invalid dynamic section.
Bug: http://b/33842263
Test: Start an app in question and check logs for warning.
Test: Run bionic-unit-test --gtest_filter=dl*:Dl*
Change-Id: I80bd51f2133b956fc04e20a6538cccd50118c1b8
Stream-mode detection for L1 in A7-core is failing for
non cache-line-size (non 64 byte) aligned addresses.
This leads to destination data getting cached unnecessarily.
This A7 issue is confirmed by ARM
This issue is solved by aligning destination address to 64 byte before
entering the loop in memcpy routine.
Though we get lower score for micro_bench memcpy when L1 cache is bypassed,
it is desirable since it avoids unnecessary eviction of other process data
from L1 which is good for overall system performance.
Higher micro_bench memcpy numbers for < 64byte alignment shows good numbers
but this is at the cost of L1 cache pollution. During memcpy/memset,
unnecessary data is filled in L1 cache, this causes eviction of other
process data from L1.
For example during msmset(0), L1 cache gets filled with 0s which should be
avoided.
Additionally, there is another issue with cortex A7 that impacts performance
for all alignments / all Android Wear versions:
Store Buffer on A7 is 32 byte which limits the 32-byte back to back stores.
In the current implementation back to back 32bytes writes is causing CPU stalls.
This issue can be solved by interleaved Loads and Stores.
This helps in avoiding CPU stalls during memcpy by utilizing efficiently the
A7 internal load and store buffers.
Change-Id: Ie5f12f2bb5d86f627686730416279057e4f5f6d0
