37c3f3c67e
Kernel headers coming from: Git: https://android.googlesource.com/kernel/common/ Branch: android-mainline Tag: android-mainline-6.4 Test: Bionic unit tests pass. Change-Id: I991f8eaa2b272a464166addb13e6bdc63734444d
204 lines
5.5 KiB
C
204 lines
5.5 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef QAIC_ACCEL_H_
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#define QAIC_ACCEL_H_
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#include "drm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
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#define QAIC_SEM_INSYNCFENCE 2
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#define QAIC_SEM_OUTSYNCFENCE 1
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#define QAIC_SEM_NOP 0
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#define QAIC_SEM_INIT 1
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#define QAIC_SEM_INC 2
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#define QAIC_SEM_DEC 3
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#define QAIC_SEM_WAIT_EQUAL 4
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#define QAIC_SEM_WAIT_GT_EQ 5
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#define QAIC_SEM_WAIT_GT_0 6
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#define QAIC_TRANS_UNDEFINED 0
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#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
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#define QAIC_TRANS_PASSTHROUGH_TO_USR 2
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#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
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#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
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#define QAIC_TRANS_DMA_XFER_FROM_USR 5
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#define QAIC_TRANS_DMA_XFER_TO_DEV 6
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#define QAIC_TRANS_ACTIVATE_FROM_USR 7
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#define QAIC_TRANS_ACTIVATE_FROM_DEV 8
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#define QAIC_TRANS_ACTIVATE_TO_DEV 9
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#define QAIC_TRANS_DEACTIVATE_FROM_USR 10
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#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
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#define QAIC_TRANS_STATUS_FROM_USR 12
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#define QAIC_TRANS_STATUS_TO_USR 13
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#define QAIC_TRANS_STATUS_FROM_DEV 14
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#define QAIC_TRANS_STATUS_TO_DEV 15
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#define QAIC_TRANS_TERMINATE_FROM_DEV 16
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#define QAIC_TRANS_TERMINATE_TO_DEV 17
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#define QAIC_TRANS_DMA_XFER_CONT 18
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#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
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#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
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struct qaic_manage_trans_hdr {
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__u32 type;
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__u32 len;
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};
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struct qaic_manage_trans_passthrough {
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struct qaic_manage_trans_hdr hdr;
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__u8 data[];
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};
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struct qaic_manage_trans_dma_xfer {
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struct qaic_manage_trans_hdr hdr;
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__u32 tag;
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__u32 pad;
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__u64 addr;
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__u64 size;
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};
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struct qaic_manage_trans_activate_to_dev {
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struct qaic_manage_trans_hdr hdr;
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__u32 queue_size;
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__u32 eventfd;
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__u32 options;
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__u32 pad;
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};
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struct qaic_manage_trans_activate_from_dev {
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struct qaic_manage_trans_hdr hdr;
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__u32 status;
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__u32 dbc_id;
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__u64 options;
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};
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struct qaic_manage_trans_deactivate {
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struct qaic_manage_trans_hdr hdr;
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__u32 dbc_id;
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__u32 pad;
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};
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struct qaic_manage_trans_status_to_dev {
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struct qaic_manage_trans_hdr hdr;
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};
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struct qaic_manage_trans_status_from_dev {
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struct qaic_manage_trans_hdr hdr;
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__u16 major;
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__u16 minor;
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__u32 status;
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__u64 status_flags;
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};
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struct qaic_manage_msg {
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__u32 len;
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__u32 count;
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__u64 data;
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};
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struct qaic_create_bo {
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__u64 size;
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__u32 handle;
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__u32 pad;
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};
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struct qaic_mmap_bo {
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__u32 handle;
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__u32 pad;
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__u64 offset;
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};
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struct qaic_sem {
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__u16 val;
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__u8 index;
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__u8 presync;
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__u8 cmd;
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__u8 flags;
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__u16 pad;
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};
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struct qaic_attach_slice_entry {
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__u64 size;
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struct qaic_sem sem0;
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struct qaic_sem sem1;
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struct qaic_sem sem2;
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struct qaic_sem sem3;
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__u64 dev_addr;
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__u64 db_addr;
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__u32 db_data;
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__u32 db_len;
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__u64 offset;
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};
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struct qaic_attach_slice_hdr {
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__u32 count;
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__u32 dbc_id;
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__u32 handle;
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__u32 dir;
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__u64 size;
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};
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struct qaic_attach_slice {
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struct qaic_attach_slice_hdr hdr;
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__u64 data;
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};
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struct qaic_execute_entry {
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__u32 handle;
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__u32 dir;
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};
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struct qaic_partial_execute_entry {
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__u32 handle;
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__u32 dir;
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__u64 resize;
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};
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struct qaic_execute_hdr {
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__u32 count;
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__u32 dbc_id;
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};
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struct qaic_execute {
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struct qaic_execute_hdr hdr;
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__u64 data;
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};
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struct qaic_wait {
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__u32 handle;
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__u32 timeout;
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__u32 dbc_id;
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__u32 pad;
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};
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struct qaic_perf_stats_hdr {
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__u16 count;
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__u16 pad;
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__u32 dbc_id;
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};
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struct qaic_perf_stats {
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struct qaic_perf_stats_hdr hdr;
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__u64 data;
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};
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struct qaic_perf_stats_entry {
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__u32 handle;
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__u32 queue_level_before;
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__u32 num_queue_element;
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__u32 submit_latency_us;
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__u32 device_latency_us;
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__u32 pad;
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};
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#define DRM_QAIC_MANAGE 0x00
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#define DRM_QAIC_CREATE_BO 0x01
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#define DRM_QAIC_MMAP_BO 0x02
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#define DRM_QAIC_ATTACH_SLICE_BO 0x03
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#define DRM_QAIC_EXECUTE_BO 0x04
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#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
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#define DRM_QAIC_WAIT_BO 0x06
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#define DRM_QAIC_PERF_STATS_BO 0x07
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#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
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#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
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#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
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#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
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#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
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#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
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#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
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#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
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#ifdef __cplusplus
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}
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#endif
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#endif
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