Atomic/SMP update.
Added atomic-inline.h. Added a platform-specific memory barrier call there. Added android_atomic_acquire_cmpxchg() and android_atomic_release_store(). Not tested on Mac OS X or SH. Added memory barrier calls to linux-x86 atomics. Mac OS X has barrier functions already. sh isn't really SMP-ready. linux-arm needs work (to be done in a separate change). Updated the makefile to make the SMP state visible to the code here. Note that host binaries are NOT built with SMP enabled; while our hosts are very likely SMP, it's not worth figuring out e.g. whether it's okay to use the SSE2 mfence instruction or have to use something else. We haven't had barriers enabled in host tools before, so there's probably no need to stat now. Removed quasiatomic 64-bit calls (now part of Dalvik). Change-Id: I49e5e6c8abe70f304cdedb9d7b8e6e65f8925815
This commit is contained in:
Andy McFadden
parent
53a79a841b
commit
ac322da69e
6 changed files with 169 additions and 245 deletions
101
include/cutils/atomic-inline.h
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101
include/cutils/atomic-inline.h
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2010 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ANDROID_CUTILS_ATOMIC_INLINE_H
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#define ANDROID_CUTILS_ATOMIC_INLINE_H
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/*
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* Inline declarations and macros for some special-purpose atomic
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* operations. These are intended for rare circumstances where a
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* memory barrier needs to be issued inline rather than as a function
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* call.
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*
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* Most code should not use these.
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*
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* Anything that does include this file must set ANDROID_SMP to either
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* 0 or 1, indicating compilation for UP or SMP, respectively.
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*/
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#if !defined(ANDROID_SMP)
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# error "Must define ANDROID_SMP before including atomic-inline.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Define the full memory barrier for an SMP system. This is
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* platform-specific.
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*/
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#ifdef __arm__
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#include <machine/cpu-features.h>
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/*
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* For ARMv6K we need to issue a specific MCR instead of the DMB, since
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* that wasn't added until v7. For anything older, SMP isn't relevant.
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* Since we don't have an ARMv6K to test with, we're not going to deal
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* with that now.
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*
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* The DMB instruction is found in the ARM and Thumb2 instruction sets.
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* This will fail on plain 16-bit Thumb.
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*/
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#if defined(__ARM_HAVE_DMB)
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# define __android_membar_full_smp() \
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do { __asm__ __volatile__ ("dmb" ::: "memory"); } while (0)
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#else
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# define __android_membar_full_smp() ARM_SMP_defined_but_no_DMB()
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#endif
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#elif defined(__i386__) || defined(__x86_64__)
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/*
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* For recent x86, we can use the SSE2 mfence instruction.
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*/
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# define __android_membar_full_smp() \
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do { __asm__ __volatile__ ("mfence" ::: "memory"); } while (0)
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#else
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/*
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* Implementation not defined for this platform. Hopefully we're building
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* in uniprocessor mode.
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*/
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# define __android_membar_full_smp() SMP_barrier_not_defined_for_platform()
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#endif
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/*
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* Full barrier. On uniprocessors this is just a compiler reorder barrier,
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* which ensures that the statements appearing above the barrier in the C/C++
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* code will be issued after the statements appearing below the barrier.
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*
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* For SMP this also includes a memory barrier instruction. On an ARM
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* CPU this means that the current core will flush pending writes, wait
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* for pending reads to complete, and discard any cached reads that could
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* be stale. Other CPUs may do less, but the end result is equivalent.
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*/
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#if ANDROID_SMP != 0
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# define android_membar_full() __android_membar_full_smp()
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#else
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# define android_membar_full() \
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do { __asm__ __volatile__ ("" ::: "memory"); } while (0)
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#endif
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // ANDROID_CUTILS_ATOMIC_INLINE_H
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@ -25,10 +25,8 @@ extern "C" {
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#endif
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/*
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* NOTE: memory shared between threads is synchronized by all atomic operations
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* below, this means that no explicit memory barrier is required: all reads or
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* writes issued before android_atomic_* operations are guaranteed to complete
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* before the atomic operation takes place.
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* Unless otherwise noted, the operations below perform a full fence before
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* the atomic operation on SMP systems ("release" semantics).
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*/
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void android_atomic_write(int32_t value, volatile int32_t* addr);
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@ -37,7 +35,6 @@ void android_atomic_write(int32_t value, volatile int32_t* addr);
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* all these atomic operations return the previous value
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*/
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int32_t android_atomic_inc(volatile int32_t* addr);
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int32_t android_atomic_dec(volatile int32_t* addr);
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@ -48,30 +45,32 @@ int32_t android_atomic_or(int32_t value, volatile int32_t* addr);
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int32_t android_atomic_swap(int32_t value, volatile int32_t* addr);
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/*
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* NOTE: Two "quasiatomic" operations on the exact same memory address
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* are guaranteed to operate atomically with respect to each other,
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* but no guarantees are made about quasiatomic operations mixed with
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* non-quasiatomic operations on the same address, nor about
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* quasiatomic operations that are performed on partially-overlapping
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* memory.
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* cmpxchg returns zero if the new value was successfully written. This
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* will only happen when *addr == oldvalue.
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*
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* (The return value is inverted from implementations on other platforms, but
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* matches the ARM ldrex/strex sematics. Note also this is a compare-and-set
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* operation, not a compare-and-exchange operation, since we don't return
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* the original value.)
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*/
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int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr);
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int64_t android_quasiatomic_read_64(volatile int64_t* addr);
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/*
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* cmpxchg return a non zero value if the exchange was NOT performed,
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* in other words if oldvalue != *addr
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*/
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int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr);
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int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
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volatile int64_t* addr);
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/*
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* Same basic operation as android_atomic_cmpxchg, but with "acquire"
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* semantics. The memory barrier, if required, is performed after the
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* new value is stored. Useful for acquiring a spin lock.
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*/
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int android_atomic_acquire_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr);
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/*
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* Perform an atomic store with "release" semantics. The memory barrier,
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* if required, is performed before the store instruction. Useful for
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* releasing a spin lock.
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*/
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#define android_atomic_release_store android_atomic_write
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#ifdef __cplusplus
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} // extern "C"
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#endif
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@ -16,6 +16,13 @@
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LOCAL_PATH := $(my-dir)
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include $(CLEAR_VARS)
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ifeq ($(TARGET_CPU_SMP),true)
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targetSmpFlag := -DANDROID_SMP=1
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else
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targetSmpFlag := -DANDROID_SMP=0
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endif
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hostSmpFlag := -DANDROID_SMP=0
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commonSources := \
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array.c \
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hashmap.c \
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@ -80,6 +87,7 @@ LOCAL_MODULE := libcutils
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LOCAL_SRC_FILES := $(commonSources) $(commonHostSources)
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LOCAL_LDLIBS := -lpthread
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LOCAL_STATIC_LIBRARIES := liblog
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LOCAL_CFLAGS += $(hostSmpFlag)
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include $(BUILD_HOST_STATIC_LIBRARY)
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@ -92,6 +100,7 @@ LOCAL_MODULE := libcutils
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LOCAL_SRC_FILES := $(commonSources) $(commonHostSources) memory.c dlmalloc_stubs.c
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LOCAL_LDLIBS := -lpthread
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LOCAL_SHARED_LIBRARIES := liblog
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LOCAL_CFLAGS += $(targetSmpFlag)
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include $(BUILD_SHARED_LIBRARY)
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else #!sim
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@ -114,12 +123,14 @@ endif # !arm
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LOCAL_C_INCLUDES := $(KERNEL_HEADERS)
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LOCAL_STATIC_LIBRARIES := liblog
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LOCAL_CFLAGS += $(targetSmpFlag)
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include $(BUILD_STATIC_LIBRARY)
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include $(CLEAR_VARS)
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LOCAL_MODULE := libcutils
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LOCAL_WHOLE_STATIC_LIBRARIES := libcutils
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LOCAL_SHARED_LIBRARIES := liblog
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LOCAL_CFLAGS += $(targetSmpFlag)
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include $(BUILD_SHARED_LIBRARY)
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endif #!sim
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@ -14,6 +14,8 @@
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* limitations under the License.
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*/
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/* TODO: insert memory barriers on SMP */
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#include <machine/cpu-features.h>
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/*
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@ -43,6 +45,8 @@
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.global android_atomic_cmpxchg
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.type android_atomic_cmpxchg, %function
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.global android_atomic_acquire_cmpxchg
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.type android_atomic_acquire_cmpxchg, %function
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/*
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* ----------------------------------------------------------------------------
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@ -237,7 +241,7 @@ android_atomic_or:
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/* replaced swp instruction with ldrex/strex for ARMv6 & ARMv7 */
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android_atomic_swap:
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#if defined (_ARM_HAVE_LDREX_STREX)
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#if defined (__ARM_HAVE_LDREX_STREX)
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1: ldrex r2, [r1]
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strex r3, r0, [r1]
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teq r3, #0
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* output: r0 = 0 (xchg done) or non-zero (xchg not done)
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*/
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android_atomic_acquire_cmpxchg:
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android_atomic_cmpxchg:
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.fnstart
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.save {r4, lr}
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@ -282,10 +287,3 @@ android_atomic_cmpxchg:
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bx lr
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.fnend
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/*
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* ----------------------------------------------------------------------------
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* android_atomic_cmpxchg_64
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* input: r0-r1=oldvalue, r2-r3=newvalue, arg4 (on stack)=address
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* output: r0 = 0 (xchg done) or non-zero (xchg not done)
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*/
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/* TODO: NEED IMPLEMENTATION FOR THIS ARCHITECTURE */
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@ -118,42 +118,8 @@ int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue,
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return result;
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}
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int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
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int64_t oldValue;
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pthread_mutex_t* lock = SWAP_LOCK(addr);
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pthread_mutex_lock(lock);
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oldValue = *addr;
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*addr = value;
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pthread_mutex_unlock(lock);
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return oldValue;
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int android_atomic_acquire_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr) {
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return android_atomic_cmpxchg(oldValue, newValue, addr);
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}
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int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
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volatile int64_t* addr) {
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int result;
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pthread_mutex_t* lock = SWAP_LOCK(addr);
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pthread_mutex_lock(lock);
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if (*addr == oldvalue) {
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*addr = newvalue;
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result = 0;
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} else {
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result = 1;
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}
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pthread_mutex_unlock(lock);
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return result;
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}
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int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
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int64_t result;
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pthread_mutex_t* lock = SWAP_LOCK(addr);
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pthread_mutex_lock(lock);
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result = *addr;
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pthread_mutex_unlock(lock);
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return result;
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}
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@ -15,6 +15,7 @@
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*/
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#include <cutils/atomic.h>
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#include <cutils/atomic-inline.h>
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#ifdef HAVE_WIN32_THREADS
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#include <windows.h>
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#else
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@ -70,40 +71,19 @@ int32_t android_atomic_swap(int32_t value, volatile int32_t* addr) {
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}
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int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue, volatile int32_t* addr) {
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/* OS X CAS returns zero on failure; invert to return zero on success */
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return OSAtomicCompareAndSwap32Barrier(oldvalue, newvalue, (int32_t*)addr) == 0;
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}
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#if defined(__ppc__) \
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|| defined(__PPC__) \
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|| defined(__powerpc__) \
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|| defined(__powerpc) \
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|| defined(__POWERPC__) \
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|| defined(_M_PPC) \
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|| defined(__PPC)
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#define NEED_QUASIATOMICS 1
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#else
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int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
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volatile int64_t* addr) {
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return OSAtomicCompareAndSwap64Barrier(oldvalue, newvalue,
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(int64_t*)addr) == 0;
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int android_atomic_acquire_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr) {
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int result = (OSAtomicCompareAndSwap32(oldvalue, newvalue, (int32_t*)addr) == 0);
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if (!result) {
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/* success, perform barrier */
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OSMemoryBarrier();
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}
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}
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int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
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int64_t oldValue;
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do {
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oldValue = *addr;
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} while (android_quasiatomic_cmpxchg_64(oldValue, value, addr));
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return oldValue;
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}
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int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
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return OSAtomicAdd64Barrier(0, addr);
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}
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#endif
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/*****************************************************************************/
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#elif defined(__i386__) || defined(__x86_64__)
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@ -163,6 +143,7 @@ int32_t android_atomic_swap(int32_t value, volatile int32_t* addr) {
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}
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int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue, volatile int32_t* addr) {
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android_membar_full();
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int xchg;
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asm volatile
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(
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@ -175,75 +156,25 @@ int android_atomic_cmpxchg(int32_t oldvalue, int32_t newvalue, volatile int32_t*
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return xchg;
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}
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#define NEED_QUASIATOMICS 1
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int android_atomic_acquire_cmpxchg(int32_t oldvalue, int32_t newvalue,
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volatile int32_t* addr) {
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int xchg;
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asm volatile
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(
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" lock; cmpxchg %%ecx, (%%edx);"
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" setne %%al;"
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" andl $1, %%eax"
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: "=a" (xchg)
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: "a" (oldvalue), "c" (newvalue), "d" (addr)
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);
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android_membar_full();
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return xchg;
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}
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/*****************************************************************************/
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#elif __arm__
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// Most of the implementation is in atomic-android-arm.s.
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// on the device, we implement the 64-bit atomic operations through
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// mutex locking. normally, this is bad because we must initialize
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// a pthread_mutex_t before being able to use it, and this means
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// having to do an initialization check on each function call, and
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// that's where really ugly things begin...
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//
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// BUT, as a special twist, we take advantage of the fact that in our
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// pthread library, a mutex is simply a volatile word whose value is always
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// initialized to 0. In other words, simply declaring a static mutex
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// object initializes it !
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//
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// another twist is that we use a small array of mutexes to dispatch
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// the contention locks from different memory addresses
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//
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#include <pthread.h>
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#define SWAP_LOCK_COUNT 32U
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static pthread_mutex_t _swap_locks[SWAP_LOCK_COUNT];
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#define SWAP_LOCK(addr) \
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&_swap_locks[((unsigned)(void*)(addr) >> 3U) % SWAP_LOCK_COUNT]
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int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
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int64_t oldValue;
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pthread_mutex_t* lock = SWAP_LOCK(addr);
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pthread_mutex_lock(lock);
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oldValue = *addr;
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*addr = value;
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pthread_mutex_unlock(lock);
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return oldValue;
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}
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int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
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volatile int64_t* addr) {
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int result;
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pthread_mutex_t* lock = SWAP_LOCK(addr);
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||||
|
||||
pthread_mutex_lock(lock);
|
||||
|
||||
if (*addr == oldvalue) {
|
||||
*addr = newvalue;
|
||||
result = 0;
|
||||
} else {
|
||||
result = 1;
|
||||
}
|
||||
pthread_mutex_unlock(lock);
|
||||
return result;
|
||||
}
|
||||
|
||||
int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
|
||||
int64_t result;
|
||||
pthread_mutex_t* lock = SWAP_LOCK(addr);
|
||||
|
||||
pthread_mutex_lock(lock);
|
||||
result = *addr;
|
||||
pthread_mutex_unlock(lock);
|
||||
return result;
|
||||
}
|
||||
// implementation for ARM is in atomic-android-arm.s.
|
||||
|
||||
/*****************************************************************************/
|
||||
#elif __sh__
|
||||
|
|
@ -255,85 +186,3 @@ int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
|
|||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if NEED_QUASIATOMICS
|
||||
|
||||
/* Note that a spinlock is *not* a good idea in general
|
||||
* since they can introduce subtle issues. For example,
|
||||
* a real-time thread trying to acquire a spinlock already
|
||||
* acquired by another thread will never yeld, making the
|
||||
* CPU loop endlessly!
|
||||
*
|
||||
* However, this code is only used on the Linux simulator
|
||||
* so it's probably ok for us.
|
||||
*
|
||||
* The alternative is to use a pthread mutex, but
|
||||
* these must be initialized before being used, and
|
||||
* then you have the problem of lazily initializing
|
||||
* a mutex without any other synchronization primitive.
|
||||
*/
|
||||
|
||||
/* global spinlock for all 64-bit quasiatomic operations */
|
||||
static int32_t quasiatomic_spinlock = 0;
|
||||
|
||||
int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
|
||||
volatile int64_t* addr) {
|
||||
int result;
|
||||
|
||||
while (android_atomic_cmpxchg(0, 1, &quasiatomic_spinlock)) {
|
||||
#ifdef HAVE_WIN32_THREADS
|
||||
Sleep(0);
|
||||
#else
|
||||
sched_yield();
|
||||
#endif
|
||||
}
|
||||
|
||||
if (*addr == oldvalue) {
|
||||
*addr = newvalue;
|
||||
result = 0;
|
||||
} else {
|
||||
result = 1;
|
||||
}
|
||||
|
||||
android_atomic_swap(0, &quasiatomic_spinlock);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
|
||||
int64_t result;
|
||||
|
||||
while (android_atomic_cmpxchg(0, 1, &quasiatomic_spinlock)) {
|
||||
#ifdef HAVE_WIN32_THREADS
|
||||
Sleep(0);
|
||||
#else
|
||||
sched_yield();
|
||||
#endif
|
||||
}
|
||||
|
||||
result = *addr;
|
||||
android_atomic_swap(0, &quasiatomic_spinlock);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
|
||||
int64_t result;
|
||||
|
||||
while (android_atomic_cmpxchg(0, 1, &quasiatomic_spinlock)) {
|
||||
#ifdef HAVE_WIN32_THREADS
|
||||
Sleep(0);
|
||||
#else
|
||||
sched_yield();
|
||||
#endif
|
||||
}
|
||||
|
||||
result = *addr;
|
||||
*addr = value;
|
||||
android_atomic_swap(0, &quasiatomic_spinlock);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue